Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31949	1		T1	20		T2	100		T21	13
auto[1]	66	1		T28	6		T31	5		T272	1
auto[2]	73	1		T28	9		T182	3		T191	1
auto[3]	261	1		T21	3		T28	11		T27	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8088	1		T1	5		T2	25		T21	3
evic_idx[1]	8088	1		T1	5		T2	25		T21	3
evic_idx[2]	8085	1		T1	5		T2	25		T21	3
evic_idx[3]	8088	1		T1	5		T2	25		T21	7

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	31314	1		T2	100		T21	16		T28	27
evic_op[2]	395	1		T23	1		T27	1		T220	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7755	1		T2	25		T21	2		T99	163
evic_idx[0]	evic_op[1]	auto[1]	11	1		T28	2		T31	1		T392	1
evic_idx[0]	evic_op[1]	auto[2]	7	1		T28	3		T393	1		T394	2
evic_idx[0]	evic_op[1]	auto[3]	56	1		T21	1		T28	2		T278	5
evic_idx[0]	evic_op[2]	auto[0]	79	1		T220	1		T34	1		T275	7
evic_idx[0]	evic_op[2]	auto[1]	3	1		T395	1		T396	1		T397	1
evic_idx[0]	evic_op[2]	auto[2]	9	1		T191	1		T272	3		T192	1
evic_idx[0]	evic_op[2]	auto[3]	8	1		T182	1		T191	1		T398	1
evic_idx[1]	evic_op[1]	auto[0]	7759	1		T2	25		T21	3		T28	1
evic_idx[1]	evic_op[1]	auto[1]	14	1		T28	2		T31	1		T399	2
evic_idx[1]	evic_op[1]	auto[2]	5	1		T28	2		T393	2		T394	1
evic_idx[1]	evic_op[1]	auto[3]	55	1		T28	3		T278	6		T400	3
evic_idx[1]	evic_op[2]	auto[0]	75	1		T34	1		T275	7		T134	1
evic_idx[1]	evic_op[2]	auto[1]	5	1		T401	1		T402	1		T403	1
evic_idx[1]	evic_op[2]	auto[2]	5	1		T182	2		T404	1		T395	1
evic_idx[1]	evic_op[2]	auto[3]	10	1		T29	1		T405	1		T406	1
evic_idx[2]	evic_op[1]	auto[0]	7756	1		T2	25		T21	3		T99	163
evic_idx[2]	evic_op[1]	auto[1]	14	1		T28	1		T31	3		T399	2
evic_idx[2]	evic_op[1]	auto[2]	5	1		T28	2		T393	1		T394	2
evic_idx[2]	evic_op[1]	auto[3]	52	1		T28	4		T278	8		T400	1
evic_idx[2]	evic_op[2]	auto[0]	77	1		T34	1		T275	7		T134	1
evic_idx[2]	evic_op[2]	auto[1]	4	1		T396	1		T407	1		T408	1
evic_idx[2]	evic_op[2]	auto[2]	5	1		T272	1		T192	1		T395	1
evic_idx[2]	evic_op[2]	auto[3]	12	1		T27	1		T409	1		T410	1
evic_idx[3]	evic_op[1]	auto[0]	7758	1		T2	25		T21	5		T99	163
evic_idx[3]	evic_op[1]	auto[1]	10	1		T28	1		T392	2		T411	1
evic_idx[3]	evic_op[1]	auto[2]	4	1		T28	2		T393	1		T394	1
evic_idx[3]	evic_op[1]	auto[3]	53	1		T21	2		T28	2		T278	9
evic_idx[3]	evic_op[2]	auto[0]	78	1		T23	1		T34	1		T275	7
evic_idx[3]	evic_op[2]	auto[1]	5	1		T272	1		T396	1		T412	1
evic_idx[3]	evic_op[2]	auto[2]	5	1		T182	1		T192	1		T404	1
evic_idx[3]	evic_op[2]	auto[3]	15	1		T30	1		T121	1		T307	1