Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	33635	1		T92	15451		T330	2747		T331	15437
rd_lvl[2]	45726	1		T332	2170		T92	11264		T333	10944
rd_lvl[3]	12256	1		T332	2187		T333	360		T334	4041
rd_lvl[4]	38102	1		T40	4365		T223	870		T332	707
rd_lvl[5]	16019	1		T40	947		T223	139		T332	1810
rd_lvl[6]	18080	1		T40	113		T223	1		T332	2347
rd_lvl[7]	7001	1		T40	28		T223	39		T332	132
rd_lvl[8]	12343	1		T40	141		T223	2		T332	132
rd_lvl[9]	6003	1		T5	320		T274	293		T335	435
rd_lvl[10]	11809	1		T5	1324		T274	1444		T335	1111
rd_lvl[11]	2004	1		T39	308		T336	156		T337	401
rd_lvl[12]	6207	1		T223	38		T320	97		T39	469
rd_lvl[13]	2956	1		T6	462		T336	89		T338	216
rd_lvl[14]	7307	1		T6	1160		T39	10		T319	348
rd_lvl[15]	3803	1		T37	136		T38	337		T319	159