Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	347123	1		T1	2		T2	1		T3	2
all_pins[1]	347123	1		T1	2		T2	1		T3	2
all_pins[2]	347123	1		T1	2		T2	1		T3	2
all_pins[3]	347123	1		T1	2		T2	1		T3	2
all_pins[4]	347123	1		T1	2		T2	1		T3	2
all_pins[5]	347123	1		T1	2		T2	1		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1726287	1		T1	12		T2	6		T3	12
values[0x1]	356451	1		T5	3288		T6	3244		T26	1664
transitions[0x0=>0x1]	315374	1		T5	3288		T6	3244		T26	1664
transitions[0x1=>0x0]	315355	1		T5	3288		T6	3244		T26	1664

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	346948	1		T1	2		T2	1		T3	2
all_pins[0]	values[0x1]	175	1		T255	1		T256	6		T257	2
all_pins[0]	transitions[0x0=>0x1]	76	1		T256	4		T257	2		T326	2
all_pins[0]	transitions[0x1=>0x0]	64	1		T255	3		T257	3		T325	3
all_pins[1]	values[0x0]	346960	1		T1	2		T2	1		T3	2
all_pins[1]	values[0x1]	163	1		T255	4		T256	2		T257	3
all_pins[1]	transitions[0x0=>0x1]	143	1		T255	3		T256	2		T257	3
all_pins[1]	transitions[0x1=>0x0]	5129	1		T37	1245		T38	241		T319	11
all_pins[2]	values[0x0]	341974	1		T1	2		T2	1		T3	2
all_pins[2]	values[0x1]	5149	1		T37	1245		T38	241		T319	11
all_pins[2]	transitions[0x0=>0x1]	35	1		T255	2		T326	4		T328	2
all_pins[2]	transitions[0x1=>0x0]	223654	1		T5	1644		T6	1622		T40	5594
all_pins[3]	values[0x0]	118355	1		T1	2		T2	1		T3	2
all_pins[3]	values[0x1]	228768	1		T5	1644		T6	1622		T40	5594
all_pins[3]	transitions[0x0=>0x1]	192976	1		T5	1644		T6	1622		T40	4079
all_pins[3]	transitions[0x1=>0x0]	86343	1		T5	1644		T6	1622		T26	1664
all_pins[4]	values[0x0]	224988	1		T1	2		T2	1		T3	2
all_pins[4]	values[0x1]	122135	1		T5	1644		T6	1622		T26	1664
all_pins[4]	transitions[0x0=>0x1]	122122	1		T5	1644		T6	1622		T26	1664
all_pins[4]	transitions[0x1=>0x0]	48	1		T255	3		T256	1		T326	1
all_pins[5]	values[0x0]	347062	1		T1	2		T2	1		T3	2
all_pins[5]	values[0x1]	61	1		T255	3		T256	1		T325	1
all_pins[5]	transitions[0x0=>0x1]	22	1		T255	2		T325	1		T329	2
all_pins[5]	transitions[0x1=>0x0]	117	1		T255	1		T256	4		T257	2