Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1		T255	4		T256	7		T257	4
all_values[1]	281	1		T255	4		T256	7		T257	4
all_values[2]	281	1		T255	4		T256	7		T257	4
all_values[3]	281	1		T255	4		T256	7		T257	4
all_values[4]	281	1		T255	4		T256	7		T257	4
all_values[5]	281	1		T255	4		T256	7		T257	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	911	1		T255	12		T256	23		T257	17
auto[1]	775	1		T255	12		T256	19		T257	7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	538	1		T255	7		T256	17		T257	7
auto[1]	1148	1		T255	17		T256	25		T257	17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1016	1		T255	15		T256	26		T257	14
auto[1]	670	1		T255	9		T256	16		T257	10

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	80	1		T255	2		T256	1		T257	1
all_values[0]	auto[0]	auto[1]	auto[1]	88	1		T256	2		T257	2		T325	2
all_values[0]	auto[1]	auto[0]	auto[1]	58	1		T255	1		T256	1		T325	3
all_values[0]	auto[1]	auto[1]	auto[1]	55	1		T255	1		T256	3		T257	1
all_values[1]	auto[0]	auto[0]	auto[1]	95	1		T255	2		T256	5		T326	2
all_values[1]	auto[0]	auto[1]	auto[1]	82	1		T255	2		T256	1		T257	1
all_values[1]	auto[1]	auto[0]	auto[1]	58	1		T256	1		T257	3		T325	3
all_values[1]	auto[1]	auto[1]	auto[1]	46	1		T325	1		T326	1		T327	1
all_values[2]	auto[0]	auto[0]	auto[0]	86	1		T256	2		T257	2		T325	2
all_values[2]	auto[0]	auto[1]	auto[0]	80	1		T255	1		T256	1		T325	4
all_values[2]	auto[1]	auto[0]	auto[1]	68	1		T255	1		T256	3		T257	2
all_values[2]	auto[1]	auto[1]	auto[1]	47	1		T255	2		T256	1		T326	4
all_values[3]	auto[0]	auto[0]	auto[0]	87	1		T256	3		T257	1		T325	1
all_values[3]	auto[0]	auto[1]	auto[0]	80	1		T255	3		T256	2		T257	2
all_values[3]	auto[1]	auto[0]	auto[1]	65	1		T255	1		T256	1		T257	1
all_values[3]	auto[1]	auto[1]	auto[1]	49	1		T256	1		T325	1		T326	1
all_values[4]	auto[0]	auto[0]	auto[0]	52	1		T255	2		T256	1		T257	2
all_values[4]	auto[0]	auto[0]	auto[1]	32	1		T326	1		T328	2		T329	1
all_values[4]	auto[0]	auto[1]	auto[0]	55	1		T255	1		T256	4		T326	2
all_values[4]	auto[0]	auto[1]	auto[1]	33	1		T257	1		T325	3		T328	1
all_values[4]	auto[1]	auto[0]	auto[1]	56	1		T255	1		T256	2		T257	1
all_values[4]	auto[1]	auto[1]	auto[1]	53	1		T325	2		T326	3		T328	2
all_values[5]	auto[0]	auto[0]	auto[0]	58	1		T256	3		T325	1		T326	5
all_values[5]	auto[0]	auto[0]	auto[1]	48	1		T255	1		T257	2		T328	1
all_values[5]	auto[0]	auto[1]	auto[0]	40	1		T256	1		T325	5		T328	1
all_values[5]	auto[0]	auto[1]	auto[1]	20	1		T255	1		T328	1		T329	1
all_values[5]	auto[1]	auto[0]	auto[1]	68	1		T255	1		T257	2		T325	1
all_values[5]	auto[1]	auto[1]	auto[1]	47	1		T255	1		T256	3		T328	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal