| T1074 |
/workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.361824746 |
|
|
Jul 24 05:42:42 PM PDT 24 |
Jul 24 05:43:15 PM PDT 24 |
71165100 ps |
| T1075 |
/workspace/coverage/default/4.flash_ctrl_alert_test.945588947 |
|
|
Jul 24 05:37:50 PM PDT 24 |
Jul 24 05:38:04 PM PDT 24 |
52863300 ps |
| T1076 |
/workspace/coverage/default/1.flash_ctrl_mp_regions.2838198919 |
|
|
Jul 24 05:36:10 PM PDT 24 |
Jul 24 05:40:49 PM PDT 24 |
111877212800 ps |
| T1077 |
/workspace/coverage/default/8.flash_ctrl_connect.3536089696 |
|
|
Jul 24 05:39:17 PM PDT 24 |
Jul 24 05:39:34 PM PDT 24 |
60412000 ps |
| T1078 |
/workspace/coverage/default/11.flash_ctrl_phy_arb.1986091014 |
|
|
Jul 24 05:39:37 PM PDT 24 |
Jul 24 05:47:39 PM PDT 24 |
765882400 ps |
| T170 |
/workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.2891301258 |
|
|
Jul 24 05:36:12 PM PDT 24 |
Jul 24 06:21:13 PM PDT 24 |
259250108600 ps |
| T1079 |
/workspace/coverage/default/31.flash_ctrl_connect.268125299 |
|
|
Jul 24 05:42:55 PM PDT 24 |
Jul 24 05:43:11 PM PDT 24 |
90609400 ps |
| T1080 |
/workspace/coverage/default/22.flash_ctrl_connect.4237863753 |
|
|
Jul 24 05:41:57 PM PDT 24 |
Jul 24 05:42:13 PM PDT 24 |
28171900 ps |
| T1081 |
/workspace/coverage/default/3.flash_ctrl_phy_arb.2991719942 |
|
|
Jul 24 05:36:58 PM PDT 24 |
Jul 24 05:45:10 PM PDT 24 |
777794200 ps |
| T1082 |
/workspace/coverage/default/6.flash_ctrl_phy_arb.2781930540 |
|
|
Jul 24 05:38:07 PM PDT 24 |
Jul 24 05:41:24 PM PDT 24 |
188175900 ps |
| T1083 |
/workspace/coverage/default/7.flash_ctrl_intr_wr.4008364626 |
|
|
Jul 24 05:38:34 PM PDT 24 |
Jul 24 05:39:47 PM PDT 24 |
8527384700 ps |
| T1084 |
/workspace/coverage/default/38.flash_ctrl_disable.1799736482 |
|
|
Jul 24 05:43:25 PM PDT 24 |
Jul 24 05:43:47 PM PDT 24 |
15043500 ps |
| T1085 |
/workspace/coverage/default/6.flash_ctrl_disable.2458633216 |
|
|
Jul 24 05:38:20 PM PDT 24 |
Jul 24 05:38:43 PM PDT 24 |
10561500 ps |
| T1086 |
/workspace/coverage/default/15.flash_ctrl_connect.1267704931 |
|
|
Jul 24 05:40:42 PM PDT 24 |
Jul 24 05:40:59 PM PDT 24 |
77447700 ps |
| T1087 |
/workspace/coverage/default/18.flash_ctrl_prog_reset.892993994 |
|
|
Jul 24 05:41:18 PM PDT 24 |
Jul 24 05:41:32 PM PDT 24 |
71671400 ps |
| T1088 |
/workspace/coverage/default/38.flash_ctrl_hw_sec_otp.853208976 |
|
|
Jul 24 05:43:21 PM PDT 24 |
Jul 24 05:44:46 PM PDT 24 |
9946451700 ps |
| T75 |
/workspace/coverage/default/4.flash_ctrl_phy_arb_redun.1149629529 |
|
|
Jul 24 05:37:46 PM PDT 24 |
Jul 24 05:38:05 PM PDT 24 |
799291600 ps |
| T1089 |
/workspace/coverage/default/38.flash_ctrl_rw_evict.3253691585 |
|
|
Jul 24 05:43:24 PM PDT 24 |
Jul 24 05:43:54 PM PDT 24 |
88564400 ps |
| T1090 |
/workspace/coverage/default/4.flash_ctrl_prog_reset.2805110742 |
|
|
Jul 24 05:37:44 PM PDT 24 |
Jul 24 05:37:58 PM PDT 24 |
75312700 ps |
| T1091 |
/workspace/coverage/default/16.flash_ctrl_rand_ops.3558006347 |
|
|
Jul 24 05:40:43 PM PDT 24 |
Jul 24 05:54:28 PM PDT 24 |
1408398400 ps |
| T1092 |
/workspace/coverage/default/17.flash_ctrl_hw_rma_reset.1924787937 |
|
|
Jul 24 05:40:57 PM PDT 24 |
Jul 24 05:54:45 PM PDT 24 |
40117759900 ps |
| T1093 |
/workspace/coverage/default/33.flash_ctrl_smoke.3035625614 |
|
|
Jul 24 05:43:00 PM PDT 24 |
Jul 24 05:46:16 PM PDT 24 |
37078300 ps |
| T1094 |
/workspace/coverage/default/12.flash_ctrl_prog_reset.1792107101 |
|
|
Jul 24 05:39:52 PM PDT 24 |
Jul 24 05:40:05 PM PDT 24 |
60295900 ps |
| T1095 |
/workspace/coverage/default/36.flash_ctrl_connect.3201526953 |
|
|
Jul 24 05:43:17 PM PDT 24 |
Jul 24 05:43:34 PM PDT 24 |
41419900 ps |
| T1096 |
/workspace/coverage/default/13.flash_ctrl_smoke.2445794372 |
|
|
Jul 24 05:40:02 PM PDT 24 |
Jul 24 05:43:19 PM PDT 24 |
30851000 ps |
| T1097 |
/workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.4289477447 |
|
|
Jul 24 05:40:04 PM PDT 24 |
Jul 24 05:41:18 PM PDT 24 |
10022307800 ps |
| T1098 |
/workspace/coverage/default/1.flash_ctrl_prog_reset.3573144000 |
|
|
Jul 24 05:36:20 PM PDT 24 |
Jul 24 05:36:40 PM PDT 24 |
97415900 ps |
| T1099 |
/workspace/coverage/default/8.flash_ctrl_disable.2249326642 |
|
|
Jul 24 05:39:17 PM PDT 24 |
Jul 24 05:39:38 PM PDT 24 |
15785300 ps |
| T1100 |
/workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.2773452253 |
|
|
Jul 24 05:38:43 PM PDT 24 |
Jul 24 05:40:28 PM PDT 24 |
10013388900 ps |
| T1101 |
/workspace/coverage/default/0.flash_ctrl_fetch_code.3228254838 |
|
|
Jul 24 05:35:48 PM PDT 24 |
Jul 24 05:36:14 PM PDT 24 |
827678000 ps |
| T1102 |
/workspace/coverage/default/18.flash_ctrl_rand_ops.2754480713 |
|
|
Jul 24 05:41:13 PM PDT 24 |
Jul 24 05:52:42 PM PDT 24 |
431951700 ps |
| T1103 |
/workspace/coverage/default/18.flash_ctrl_rw.2950863920 |
|
|
Jul 24 05:41:16 PM PDT 24 |
Jul 24 05:53:23 PM PDT 24 |
4539063800 ps |
| T1104 |
/workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.3710147004 |
|
|
Jul 24 05:42:22 PM PDT 24 |
Jul 24 05:42:53 PM PDT 24 |
33787100 ps |
| T1105 |
/workspace/coverage/default/4.flash_ctrl_otp_reset.2919275340 |
|
|
Jul 24 05:37:28 PM PDT 24 |
Jul 24 05:39:44 PM PDT 24 |
68724800 ps |
| T1106 |
/workspace/coverage/default/5.flash_ctrl_hw_sec_otp.993052262 |
|
|
Jul 24 05:37:54 PM PDT 24 |
Jul 24 05:40:05 PM PDT 24 |
12771761300 ps |
| T1107 |
/workspace/coverage/default/1.flash_ctrl_serr_address.2175596648 |
|
|
Jul 24 05:36:17 PM PDT 24 |
Jul 24 05:37:43 PM PDT 24 |
2988792700 ps |
| T1108 |
/workspace/coverage/default/2.flash_ctrl_config_regwen.714760156 |
|
|
Jul 24 05:37:24 PM PDT 24 |
Jul 24 05:37:38 PM PDT 24 |
36601100 ps |
| T1109 |
/workspace/coverage/default/0.flash_ctrl_serr_counter.3880129812 |
|
|
Jul 24 05:35:53 PM PDT 24 |
Jul 24 05:37:36 PM PDT 24 |
4695263200 ps |
| T1110 |
/workspace/coverage/default/1.flash_ctrl_error_mp.2805361143 |
|
|
Jul 24 05:36:11 PM PDT 24 |
Jul 24 06:12:19 PM PDT 24 |
7276619000 ps |
| T1111 |
/workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.2653475685 |
|
|
Jul 24 05:38:44 PM PDT 24 |
Jul 24 05:38:57 PM PDT 24 |
118029500 ps |
| T67 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3243341817 |
|
|
Jul 24 04:55:00 PM PDT 24 |
Jul 24 04:55:18 PM PDT 24 |
43403200 ps |
| T1112 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2614499132 |
|
|
Jul 24 04:55:00 PM PDT 24 |
Jul 24 04:55:13 PM PDT 24 |
43321100 ps |
| T68 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.4096646181 |
|
|
Jul 24 04:55:04 PM PDT 24 |
Jul 24 04:55:20 PM PDT 24 |
98109100 ps |
| T255 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.82984903 |
|
|
Jul 24 04:55:17 PM PDT 24 |
Jul 24 04:55:31 PM PDT 24 |
16917500 ps |
| T1113 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3358942711 |
|
|
Jul 24 04:55:06 PM PDT 24 |
Jul 24 04:55:21 PM PDT 24 |
105234000 ps |
| T69 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1875566127 |
|
|
Jul 24 04:55:07 PM PDT 24 |
Jul 24 04:55:26 PM PDT 24 |
360520600 ps |
| T256 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.31573391 |
|
|
Jul 24 04:55:11 PM PDT 24 |
Jul 24 04:55:24 PM PDT 24 |
28263300 ps |
| T202 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1027305216 |
|
|
Jul 24 04:55:03 PM PDT 24 |
Jul 24 04:55:21 PM PDT 24 |
641700400 ps |
| T257 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.682526575 |
|
|
Jul 24 04:55:10 PM PDT 24 |
Jul 24 04:55:24 PM PDT 24 |
62528200 ps |
| T203 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2554569037 |
|
|
Jul 24 04:55:01 PM PDT 24 |
Jul 24 05:02:44 PM PDT 24 |
375113700 ps |
| T325 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1618310023 |
|
|
Jul 24 04:54:54 PM PDT 24 |
Jul 24 04:55:08 PM PDT 24 |
16424900 ps |
| T326 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.4163116230 |
|
|
Jul 24 04:55:09 PM PDT 24 |
Jul 24 04:55:24 PM PDT 24 |
17731200 ps |
| T247 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2403150165 |
|
|
Jul 24 04:54:49 PM PDT 24 |
Jul 24 04:55:23 PM PDT 24 |
1408451700 ps |
| T1114 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.952597767 |
|
|
Jul 24 04:54:58 PM PDT 24 |
Jul 24 04:55:14 PM PDT 24 |
21847500 ps |
| T232 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1358003852 |
|
|
Jul 24 04:55:01 PM PDT 24 |
Jul 24 04:55:16 PM PDT 24 |
117101200 ps |
| T249 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.674034434 |
|
|
Jul 24 04:55:06 PM PDT 24 |
Jul 24 04:55:24 PM PDT 24 |
46760400 ps |
| T248 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3343449964 |
|
|
Jul 24 04:55:03 PM PDT 24 |
Jul 24 04:55:21 PM PDT 24 |
161545100 ps |
| T237 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1873951434 |
|
|
Jul 24 04:55:03 PM PDT 24 |
Jul 24 04:55:18 PM PDT 24 |
48402100 ps |
| T328 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3754031828 |
|
|
Jul 24 04:55:04 PM PDT 24 |
Jul 24 04:55:19 PM PDT 24 |
16826700 ps |
| T250 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3389164299 |
|
|
Jul 24 04:55:00 PM PDT 24 |
Jul 24 04:55:18 PM PDT 24 |
55412000 ps |
| T238 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3512196117 |
|
|
Jul 24 04:54:43 PM PDT 24 |
Jul 24 04:54:57 PM PDT 24 |
89629000 ps |
| T1115 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1126788259 |
|
|
Jul 24 04:54:59 PM PDT 24 |
Jul 24 04:55:15 PM PDT 24 |
40010400 ps |
| T204 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2161972417 |
|
|
Jul 24 04:54:36 PM PDT 24 |
Jul 24 04:54:53 PM PDT 24 |
131590400 ps |
| T293 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3823393500 |
|
|
Jul 24 04:54:56 PM PDT 24 |
Jul 24 04:55:14 PM PDT 24 |
441970600 ps |
| T1116 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2138628498 |
|
|
Jul 24 04:55:02 PM PDT 24 |
Jul 24 04:55:18 PM PDT 24 |
38369100 ps |
| T329 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1051539225 |
|
|
Jul 24 04:55:12 PM PDT 24 |
Jul 24 04:55:25 PM PDT 24 |
18044900 ps |
| T294 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.4067125809 |
|
|
Jul 24 04:54:47 PM PDT 24 |
Jul 24 04:55:05 PM PDT 24 |
131052900 ps |
| T1117 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2345529716 |
|
|
Jul 24 04:55:00 PM PDT 24 |
Jul 24 04:55:14 PM PDT 24 |
68716200 ps |
| T1118 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3505903626 |
|
|
Jul 24 04:55:11 PM PDT 24 |
Jul 24 04:55:28 PM PDT 24 |
46511200 ps |
| T1119 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2141103486 |
|
|
Jul 24 04:55:04 PM PDT 24 |
Jul 24 04:55:20 PM PDT 24 |
39082100 ps |
| T1120 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3447830072 |
|
|
Jul 24 04:55:05 PM PDT 24 |
Jul 24 04:55:19 PM PDT 24 |
15954700 ps |
| T351 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.773073980 |
|
|
Jul 24 04:55:18 PM PDT 24 |
Jul 24 04:55:32 PM PDT 24 |
31491900 ps |
| T205 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1747979809 |
|
|
Jul 24 04:55:04 PM PDT 24 |
Jul 24 05:07:49 PM PDT 24 |
1364562100 ps |
| T1121 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.949705859 |
|
|
Jul 24 04:54:46 PM PDT 24 |
Jul 24 04:54:59 PM PDT 24 |
12163700 ps |
| T233 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2590736841 |
|
|
Jul 24 04:54:58 PM PDT 24 |
Jul 24 04:55:17 PM PDT 24 |
1622896800 ps |
| T352 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3646336101 |
|
|
Jul 24 04:54:59 PM PDT 24 |
Jul 24 04:56:05 PM PDT 24 |
2189992300 ps |
| T206 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2950023807 |
|
|
Jul 24 04:54:41 PM PDT 24 |
Jul 24 05:09:40 PM PDT 24 |
870854300 ps |
| T234 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2058844859 |
|
|
Jul 24 04:55:01 PM PDT 24 |
Jul 24 04:55:17 PM PDT 24 |
36727600 ps |
| T1122 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.679531120 |
|
|
Jul 24 04:54:31 PM PDT 24 |
Jul 24 04:54:44 PM PDT 24 |
11598000 ps |
| T235 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1880309076 |
|
|
Jul 24 04:54:53 PM PDT 24 |
Jul 24 04:55:12 PM PDT 24 |
167215400 ps |
| T327 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.3739046031 |
|
|
Jul 24 04:54:51 PM PDT 24 |
Jul 24 04:55:05 PM PDT 24 |
54257400 ps |
| T1123 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1405647422 |
|
|
Jul 24 04:55:04 PM PDT 24 |
Jul 24 04:55:19 PM PDT 24 |
19780700 ps |
| T1124 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1675248148 |
|
|
Jul 24 04:55:03 PM PDT 24 |
Jul 24 04:55:19 PM PDT 24 |
14364300 ps |
| T236 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1897178089 |
|
|
Jul 24 04:55:10 PM PDT 24 |
Jul 24 04:55:28 PM PDT 24 |
34985300 ps |
| T345 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2771246322 |
|
|
Jul 24 04:55:01 PM PDT 24 |
Jul 24 05:02:37 PM PDT 24 |
346407200 ps |
| T1125 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.44311156 |
|
|
Jul 24 04:55:11 PM PDT 24 |
Jul 24 04:55:29 PM PDT 24 |
42608600 ps |
| T1126 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.989084048 |
|
|
Jul 24 04:55:01 PM PDT 24 |
Jul 24 04:55:15 PM PDT 24 |
60698000 ps |
| T1127 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2436643100 |
|
|
Jul 24 04:55:04 PM PDT 24 |
Jul 24 04:55:35 PM PDT 24 |
250773400 ps |
| T344 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3641977619 |
|
|
Jul 24 04:54:56 PM PDT 24 |
Jul 24 05:01:26 PM PDT 24 |
675851100 ps |
| T1128 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1887516266 |
|
|
Jul 24 04:54:52 PM PDT 24 |
Jul 24 04:55:07 PM PDT 24 |
26094400 ps |
| T300 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.3056980415 |
|
|
Jul 24 04:54:52 PM PDT 24 |
Jul 24 04:55:28 PM PDT 24 |
3015944800 ps |
| T271 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1263618107 |
|
|
Jul 24 04:55:01 PM PDT 24 |
Jul 24 04:55:21 PM PDT 24 |
325475600 ps |
| T1129 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3449638174 |
|
|
Jul 24 04:54:49 PM PDT 24 |
Jul 24 04:55:02 PM PDT 24 |
34555100 ps |
| T1130 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1178599979 |
|
|
Jul 24 04:55:17 PM PDT 24 |
Jul 24 04:55:30 PM PDT 24 |
76146400 ps |
| T295 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2748344243 |
|
|
Jul 24 04:54:45 PM PDT 24 |
Jul 24 04:55:03 PM PDT 24 |
417522500 ps |
| T1131 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1151725958 |
|
|
Jul 24 04:55:05 PM PDT 24 |
Jul 24 04:55:21 PM PDT 24 |
22445500 ps |
| T1132 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.451175165 |
|
|
Jul 24 04:54:45 PM PDT 24 |
Jul 24 04:55:16 PM PDT 24 |
18041700 ps |
| T1133 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1255725500 |
|
|
Jul 24 04:54:50 PM PDT 24 |
Jul 24 04:55:06 PM PDT 24 |
37049000 ps |
| T1134 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2931702943 |
|
|
Jul 24 04:54:50 PM PDT 24 |
Jul 24 04:55:04 PM PDT 24 |
50222200 ps |
| T262 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2867378402 |
|
|
Jul 24 04:55:07 PM PDT 24 |
Jul 24 05:10:07 PM PDT 24 |
707155900 ps |
| T1135 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3020926876 |
|
|
Jul 24 04:55:02 PM PDT 24 |
Jul 24 04:55:16 PM PDT 24 |
81171800 ps |
| T1136 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1533999532 |
|
|
Jul 24 04:54:38 PM PDT 24 |
Jul 24 04:54:53 PM PDT 24 |
281078700 ps |
| T1137 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2707086645 |
|
|
Jul 24 04:55:12 PM PDT 24 |
Jul 24 04:55:41 PM PDT 24 |
208979000 ps |
| T1138 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3440304176 |
|
|
Jul 24 04:54:55 PM PDT 24 |
Jul 24 04:55:15 PM PDT 24 |
62714800 ps |
| T253 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2548231435 |
|
|
Jul 24 04:55:15 PM PDT 24 |
Jul 24 04:55:33 PM PDT 24 |
88727400 ps |
| T254 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.523720397 |
|
|
Jul 24 04:54:51 PM PDT 24 |
Jul 24 04:55:10 PM PDT 24 |
62960900 ps |
| T1139 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3356467974 |
|
|
Jul 24 04:55:07 PM PDT 24 |
Jul 24 04:55:21 PM PDT 24 |
14683700 ps |
| T1140 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2462644773 |
|
|
Jul 24 04:55:11 PM PDT 24 |
Jul 24 04:55:29 PM PDT 24 |
88985100 ps |
| T1141 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.332712205 |
|
|
Jul 24 04:54:50 PM PDT 24 |
Jul 24 04:55:04 PM PDT 24 |
23147800 ps |
| T258 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.680161342 |
|
|
Jul 24 04:54:55 PM PDT 24 |
Jul 24 04:55:15 PM PDT 24 |
243665600 ps |
| T1142 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2173390459 |
|
|
Jul 24 04:54:51 PM PDT 24 |
Jul 24 04:55:22 PM PDT 24 |
631181200 ps |
| T1143 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.386263799 |
|
|
Jul 24 04:55:00 PM PDT 24 |
Jul 24 04:55:32 PM PDT 24 |
1907925700 ps |
| T296 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.178866528 |
|
|
Jul 24 04:55:00 PM PDT 24 |
Jul 24 04:55:18 PM PDT 24 |
222849200 ps |
| T239 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.713418571 |
|
|
Jul 24 04:54:41 PM PDT 24 |
Jul 24 04:54:55 PM PDT 24 |
36076300 ps |
| T1144 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3685928976 |
|
|
Jul 24 04:54:54 PM PDT 24 |
Jul 24 04:55:09 PM PDT 24 |
34900900 ps |
| T1145 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3285248567 |
|
|
Jul 24 04:54:37 PM PDT 24 |
Jul 24 04:55:12 PM PDT 24 |
1978102600 ps |
| T1146 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.995897561 |
|
|
Jul 24 04:54:43 PM PDT 24 |
Jul 24 04:54:59 PM PDT 24 |
178620100 ps |
| T1147 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2889019030 |
|
|
Jul 24 04:54:53 PM PDT 24 |
Jul 24 04:56:03 PM PDT 24 |
2242575700 ps |
| T1148 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2846112193 |
|
|
Jul 24 04:55:12 PM PDT 24 |
Jul 24 04:55:27 PM PDT 24 |
165034300 ps |
| T1149 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3368724508 |
|
|
Jul 24 04:55:03 PM PDT 24 |
Jul 24 04:55:20 PM PDT 24 |
33951600 ps |
| T1150 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.470017394 |
|
|
Jul 24 04:55:03 PM PDT 24 |
Jul 24 04:55:20 PM PDT 24 |
67077000 ps |
| T322 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.4150107538 |
|
|
Jul 24 04:54:46 PM PDT 24 |
Jul 24 04:55:02 PM PDT 24 |
41697500 ps |
| T265 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3631781393 |
|
|
Jul 24 04:55:09 PM PDT 24 |
Jul 24 04:55:28 PM PDT 24 |
161458800 ps |
| T297 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1023773436 |
|
|
Jul 24 04:54:54 PM PDT 24 |
Jul 24 04:55:12 PM PDT 24 |
1968298300 ps |
| T1151 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3321504760 |
|
|
Jul 24 04:54:50 PM PDT 24 |
Jul 24 04:55:08 PM PDT 24 |
243514400 ps |
| T1152 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2848497163 |
|
|
Jul 24 04:54:52 PM PDT 24 |
Jul 24 04:55:38 PM PDT 24 |
33726500 ps |
| T347 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2299497274 |
|
|
Jul 24 04:54:56 PM PDT 24 |
Jul 24 05:02:34 PM PDT 24 |
557712000 ps |
| T1153 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1187712064 |
|
|
Jul 24 04:54:42 PM PDT 24 |
Jul 24 04:55:00 PM PDT 24 |
64365900 ps |
| T1154 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1572207035 |
|
|
Jul 24 04:55:11 PM PDT 24 |
Jul 24 04:55:27 PM PDT 24 |
41216300 ps |
| T1155 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3983157036 |
|
|
Jul 24 04:54:55 PM PDT 24 |
Jul 24 04:55:09 PM PDT 24 |
26176600 ps |
| T1156 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.711406823 |
|
|
Jul 24 04:54:54 PM PDT 24 |
Jul 24 04:55:07 PM PDT 24 |
14349100 ps |
| T1157 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3730719858 |
|
|
Jul 24 04:54:52 PM PDT 24 |
Jul 24 04:55:28 PM PDT 24 |
185868200 ps |
| T1158 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1422327278 |
|
|
Jul 24 04:54:54 PM PDT 24 |
Jul 24 04:55:10 PM PDT 24 |
24857700 ps |
| T1159 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3038931379 |
|
|
Jul 24 04:55:10 PM PDT 24 |
Jul 24 04:55:24 PM PDT 24 |
22706100 ps |
| T1160 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3394528687 |
|
|
Jul 24 04:55:03 PM PDT 24 |
Jul 24 04:55:19 PM PDT 24 |
128000700 ps |
| T260 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2000005402 |
|
|
Jul 24 04:55:02 PM PDT 24 |
Jul 24 05:07:44 PM PDT 24 |
4976276600 ps |
| T298 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1264474760 |
|
|
Jul 24 04:54:32 PM PDT 24 |
Jul 24 04:55:23 PM PDT 24 |
10806819600 ps |
| T1161 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.694492610 |
|
|
Jul 24 04:55:05 PM PDT 24 |
Jul 24 04:55:21 PM PDT 24 |
23622500 ps |
| T259 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3983842835 |
|
|
Jul 24 04:54:56 PM PDT 24 |
Jul 24 04:55:13 PM PDT 24 |
67552600 ps |
| T299 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3011932874 |
|
|
Jul 24 04:54:55 PM PDT 24 |
Jul 24 04:55:14 PM PDT 24 |
642527700 ps |
| T261 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.615013205 |
|
|
Jul 24 04:55:03 PM PDT 24 |
Jul 24 04:55:23 PM PDT 24 |
183175000 ps |
| T270 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2218296071 |
|
|
Jul 24 04:55:18 PM PDT 24 |
Jul 24 05:10:21 PM PDT 24 |
959358600 ps |
| T1162 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2740731003 |
|
|
Jul 24 04:55:05 PM PDT 24 |
Jul 24 04:55:22 PM PDT 24 |
177637300 ps |
| T1163 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1298554255 |
|
|
Jul 24 04:55:01 PM PDT 24 |
Jul 24 04:55:17 PM PDT 24 |
13279600 ps |
| T267 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2667238644 |
|
|
Jul 24 04:54:59 PM PDT 24 |
Jul 24 05:01:25 PM PDT 24 |
518773200 ps |
| T1164 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.4005290082 |
|
|
Jul 24 04:54:51 PM PDT 24 |
Jul 24 04:55:49 PM PDT 24 |
2594788900 ps |
| T1165 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3485734846 |
|
|
Jul 24 04:54:36 PM PDT 24 |
Jul 24 04:54:49 PM PDT 24 |
27694700 ps |
| T1166 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3526519622 |
|
|
Jul 24 04:55:02 PM PDT 24 |
Jul 24 04:55:16 PM PDT 24 |
31307300 ps |
| T349 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1142510467 |
|
|
Jul 24 04:54:50 PM PDT 24 |
Jul 24 05:02:29 PM PDT 24 |
789345800 ps |
| T1167 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.137937741 |
|
|
Jul 24 04:55:07 PM PDT 24 |
Jul 24 04:55:21 PM PDT 24 |
13117600 ps |
| T1168 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1474817712 |
|
|
Jul 24 04:54:44 PM PDT 24 |
Jul 24 04:54:58 PM PDT 24 |
20129100 ps |
| T1169 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2196003522 |
|
|
Jul 24 04:55:05 PM PDT 24 |
Jul 24 04:55:19 PM PDT 24 |
50472900 ps |
| T1170 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.417307444 |
|
|
Jul 24 04:55:02 PM PDT 24 |
Jul 24 04:55:16 PM PDT 24 |
21435400 ps |
| T1171 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1792852762 |
|
|
Jul 24 04:55:17 PM PDT 24 |
Jul 24 04:55:30 PM PDT 24 |
43712800 ps |
| T1172 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2485492643 |
|
|
Jul 24 04:55:10 PM PDT 24 |
Jul 24 04:55:27 PM PDT 24 |
113290000 ps |
| T251 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.4118325325 |
|
|
Jul 24 04:55:02 PM PDT 24 |
Jul 24 04:55:19 PM PDT 24 |
57150400 ps |
| T252 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2776024061 |
|
|
Jul 24 04:55:04 PM PDT 24 |
Jul 24 04:55:26 PM PDT 24 |
1214131000 ps |
| T301 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2661100048 |
|
|
Jul 24 04:54:54 PM PDT 24 |
Jul 24 04:55:43 PM PDT 24 |
1674805100 ps |
| T302 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.4225628532 |
|
|
Jul 24 04:54:43 PM PDT 24 |
Jul 24 04:55:03 PM PDT 24 |
187412900 ps |
| T268 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.4155364775 |
|
|
Jul 24 04:55:00 PM PDT 24 |
Jul 24 04:55:20 PM PDT 24 |
63664300 ps |
| T1173 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.4053334884 |
|
|
Jul 24 04:55:03 PM PDT 24 |
Jul 24 04:55:18 PM PDT 24 |
56642500 ps |
| T1174 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2362314223 |
|
|
Jul 24 04:55:04 PM PDT 24 |
Jul 24 04:55:23 PM PDT 24 |
216460200 ps |
| T303 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.322558435 |
|
|
Jul 24 04:54:44 PM PDT 24 |
Jul 24 04:55:02 PM PDT 24 |
354881800 ps |
| T1175 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1754057232 |
|
|
Jul 24 04:54:43 PM PDT 24 |
Jul 24 04:55:55 PM PDT 24 |
2530502400 ps |
| T1176 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2041473659 |
|
|
Jul 24 04:54:46 PM PDT 24 |
Jul 24 04:55:13 PM PDT 24 |
95022000 ps |
| T1177 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2609054095 |
|
|
Jul 24 04:55:06 PM PDT 24 |
Jul 24 04:55:21 PM PDT 24 |
53344200 ps |
| T264 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.1058946861 |
|
|
Jul 24 04:55:03 PM PDT 24 |
Jul 24 04:55:22 PM PDT 24 |
333410100 ps |
| T304 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3396682231 |
|
|
Jul 24 04:54:55 PM PDT 24 |
Jul 24 04:55:12 PM PDT 24 |
200893700 ps |
| T1178 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2390984915 |
|
|
Jul 24 04:54:59 PM PDT 24 |
Jul 24 04:55:16 PM PDT 24 |
43906000 ps |
| T1179 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1409041845 |
|
|
Jul 24 04:54:58 PM PDT 24 |
Jul 24 04:55:12 PM PDT 24 |
25147400 ps |
| T1180 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2253973463 |
|
|
Jul 24 04:55:11 PM PDT 24 |
Jul 24 04:55:25 PM PDT 24 |
18999500 ps |
| T1181 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1001207660 |
|
|
Jul 24 04:55:04 PM PDT 24 |
Jul 24 04:55:20 PM PDT 24 |
25201800 ps |
| T1182 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2444376127 |
|
|
Jul 24 04:55:15 PM PDT 24 |
Jul 24 04:55:31 PM PDT 24 |
19562300 ps |
| T1183 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.159934716 |
|
|
Jul 24 04:55:13 PM PDT 24 |
Jul 24 04:55:29 PM PDT 24 |
83191700 ps |
| T1184 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1443382322 |
|
|
Jul 24 04:55:05 PM PDT 24 |
Jul 24 04:55:20 PM PDT 24 |
20058700 ps |
| T1185 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2860582944 |
|
|
Jul 24 04:55:00 PM PDT 24 |
Jul 24 04:55:16 PM PDT 24 |
110593200 ps |
| T1186 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2367520401 |
|
|
Jul 24 04:54:53 PM PDT 24 |
Jul 24 05:02:36 PM PDT 24 |
227401000 ps |
| T1187 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.4003912961 |
|
|
Jul 24 04:55:09 PM PDT 24 |
Jul 24 04:55:23 PM PDT 24 |
45095400 ps |
| T1188 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1252350673 |
|
|
Jul 24 04:55:17 PM PDT 24 |
Jul 24 04:55:30 PM PDT 24 |
56922600 ps |
| T1189 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2504460058 |
|
|
Jul 24 04:55:05 PM PDT 24 |
Jul 24 04:55:35 PM PDT 24 |
243673800 ps |
| T1190 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2170381672 |
|
|
Jul 24 04:55:04 PM PDT 24 |
Jul 24 04:55:21 PM PDT 24 |
18292800 ps |
| T1191 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1831138604 |
|
|
Jul 24 04:55:11 PM PDT 24 |
Jul 24 04:55:25 PM PDT 24 |
51537600 ps |
| T1192 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3026477703 |
|
|
Jul 24 04:54:55 PM PDT 24 |
Jul 24 04:55:16 PM PDT 24 |
34671200 ps |
| T1193 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3289581912 |
|
|
Jul 24 04:54:56 PM PDT 24 |
Jul 24 04:55:12 PM PDT 24 |
22434500 ps |
| T1194 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1985678614 |
|
|
Jul 24 04:54:37 PM PDT 24 |
Jul 24 04:54:51 PM PDT 24 |
24456600 ps |
| T1195 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.3356785826 |
|
|
Jul 24 04:54:45 PM PDT 24 |
Jul 24 04:54:58 PM PDT 24 |
44223900 ps |
| T1196 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.477998270 |
|
|
Jul 24 04:55:02 PM PDT 24 |
Jul 24 05:02:43 PM PDT 24 |
179026200 ps |
| T1197 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2698235789 |
|
|
Jul 24 04:55:04 PM PDT 24 |
Jul 24 04:55:18 PM PDT 24 |
42962200 ps |
| T1198 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1583603347 |
|
|
Jul 24 04:55:18 PM PDT 24 |
Jul 24 04:55:32 PM PDT 24 |
17750500 ps |
| T1199 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2785900169 |
|
|
Jul 24 04:55:05 PM PDT 24 |
Jul 24 04:55:25 PM PDT 24 |
121561200 ps |
| T1200 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.141245478 |
|
|
Jul 24 04:55:07 PM PDT 24 |
Jul 24 04:55:26 PM PDT 24 |
511251100 ps |
| T1201 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3510456117 |
|
|
Jul 24 04:54:51 PM PDT 24 |
Jul 24 04:55:07 PM PDT 24 |
23979900 ps |
| T1202 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2293044687 |
|
|
Jul 24 04:54:51 PM PDT 24 |
Jul 24 04:55:22 PM PDT 24 |
20518300 ps |
| T1203 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.356265342 |
|
|
Jul 24 04:55:10 PM PDT 24 |
Jul 24 04:55:23 PM PDT 24 |
58673900 ps |
| T1204 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1370418988 |
|
|
Jul 24 04:55:01 PM PDT 24 |
Jul 24 04:55:14 PM PDT 24 |
16663400 ps |
| T348 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1338579538 |
|
|
Jul 24 04:55:04 PM PDT 24 |
Jul 24 05:01:31 PM PDT 24 |
180699300 ps |
| T1205 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.1409180863 |
|
|
Jul 24 04:55:26 PM PDT 24 |
Jul 24 04:55:40 PM PDT 24 |
18610800 ps |
| T1206 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2791780881 |
|
|
Jul 24 04:54:49 PM PDT 24 |
Jul 24 04:55:03 PM PDT 24 |
14001500 ps |
| T1207 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2418136661 |
|
|
Jul 24 04:54:41 PM PDT 24 |
Jul 24 04:54:56 PM PDT 24 |
162015100 ps |
| T1208 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3932903098 |
|
|
Jul 24 04:55:06 PM PDT 24 |
Jul 24 04:55:22 PM PDT 24 |
19361900 ps |
| T1209 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.210982887 |
|
|
Jul 24 04:55:15 PM PDT 24 |
Jul 24 04:55:29 PM PDT 24 |
23240500 ps |
| T1210 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.492779025 |
|
|
Jul 24 04:55:00 PM PDT 24 |
Jul 24 04:55:16 PM PDT 24 |
21341600 ps |
| T1211 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2338683698 |
|
|
Jul 24 04:54:56 PM PDT 24 |
Jul 24 04:55:15 PM PDT 24 |
271544600 ps |
| T1212 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.808096948 |
|
|
Jul 24 04:55:03 PM PDT 24 |
Jul 24 04:55:18 PM PDT 24 |
15077000 ps |
| T1213 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3432855757 |
|
|
Jul 24 04:55:05 PM PDT 24 |
Jul 24 04:55:23 PM PDT 24 |
272218700 ps |
| T240 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2578113243 |
|
|
Jul 24 04:54:44 PM PDT 24 |
Jul 24 04:54:58 PM PDT 24 |
18891800 ps |
| T1214 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2354421226 |
|
|
Jul 24 04:55:04 PM PDT 24 |
Jul 24 04:55:18 PM PDT 24 |
18180300 ps |
| T1215 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2807122002 |
|
|
Jul 24 04:55:02 PM PDT 24 |
Jul 24 04:55:16 PM PDT 24 |
45258600 ps |
| T1216 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.483073598 |
|
|
Jul 24 04:54:55 PM PDT 24 |
Jul 24 04:55:08 PM PDT 24 |
92935600 ps |
| T266 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.4148918987 |
|
|
Jul 24 04:54:57 PM PDT 24 |
Jul 24 04:55:19 PM PDT 24 |
52405000 ps |
| T1217 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2693373442 |
|
|
Jul 24 04:55:16 PM PDT 24 |
Jul 24 04:55:30 PM PDT 24 |
70697000 ps |
| T1218 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.4072185505 |
|
|
Jul 24 04:55:17 PM PDT 24 |
Jul 24 04:55:34 PM PDT 24 |
116614900 ps |
| T1219 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2251098380 |
|
|
Jul 24 04:55:04 PM PDT 24 |
Jul 24 04:55:22 PM PDT 24 |
218176300 ps |
| T1220 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.159770293 |
|
|
Jul 24 04:55:05 PM PDT 24 |
Jul 24 04:55:21 PM PDT 24 |
16866200 ps |
| T1221 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2233145830 |
|
|
Jul 24 04:54:57 PM PDT 24 |
Jul 24 05:10:08 PM PDT 24 |
13759021900 ps |
| T1222 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1957131556 |
|
|
Jul 24 04:55:09 PM PDT 24 |
Jul 24 04:55:28 PM PDT 24 |
830979100 ps |
| T1223 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.4243946117 |
|
|
Jul 24 04:54:57 PM PDT 24 |
Jul 24 04:55:13 PM PDT 24 |
109600600 ps |
| T346 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.655197878 |
|
|
Jul 24 04:54:42 PM PDT 24 |
Jul 24 05:01:09 PM PDT 24 |
171211100 ps |
| T1224 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2693268455 |
|
|
Jul 24 04:54:54 PM PDT 24 |
Jul 24 04:56:22 PM PDT 24 |
3811148700 ps |
| T1225 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3479379138 |
|
|
Jul 24 04:54:47 PM PDT 24 |
Jul 24 04:55:05 PM PDT 24 |
200855300 ps |
| T1226 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1899498394 |
|
|
Jul 24 04:55:02 PM PDT 24 |
Jul 24 04:55:16 PM PDT 24 |
50060400 ps |
| T1227 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2977506304 |
|
|
Jul 24 04:54:37 PM PDT 24 |
Jul 24 04:55:08 PM PDT 24 |
53806200 ps |
| T1228 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2764793929 |
|
|
Jul 24 04:55:17 PM PDT 24 |
Jul 24 04:55:31 PM PDT 24 |
17442200 ps |
| T263 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1669025018 |
|
|
Jul 24 04:55:00 PM PDT 24 |
Jul 24 04:55:20 PM PDT 24 |
307791300 ps |
| T1229 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.3252913370 |
|
|
Jul 24 04:55:10 PM PDT 24 |
Jul 24 04:55:24 PM PDT 24 |
14974200 ps |
| T342 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1303557367 |
|
|
Jul 24 04:54:54 PM PDT 24 |
Jul 24 05:07:34 PM PDT 24 |
699743100 ps |
| T1230 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.1829438238 |
|
|
Jul 24 04:54:31 PM PDT 24 |
Jul 24 04:54:47 PM PDT 24 |
23844200 ps |
| T1231 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1195796532 |
|
|
Jul 24 04:55:02 PM PDT 24 |
Jul 24 04:55:19 PM PDT 24 |
48132000 ps |
| T1232 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.4120138945 |
|
|
Jul 24 04:54:52 PM PDT 24 |
Jul 24 04:55:07 PM PDT 24 |
84966500 ps |
| T1233 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2252441186 |
|
|
Jul 24 04:55:00 PM PDT 24 |
Jul 24 04:55:19 PM PDT 24 |
92127100 ps |
| T1234 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.705174577 |
|
|
Jul 24 04:55:00 PM PDT 24 |
Jul 24 04:55:14 PM PDT 24 |
43967800 ps |
| T1235 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3848901034 |
|
|
Jul 24 04:54:51 PM PDT 24 |
Jul 24 04:55:05 PM PDT 24 |
90532100 ps |
| T1236 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2262122259 |
|
|
Jul 24 04:55:03 PM PDT 24 |
Jul 24 04:55:17 PM PDT 24 |
39612800 ps |
| T1237 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2476986916 |
|
|
Jul 24 04:54:54 PM PDT 24 |
Jul 24 04:55:09 PM PDT 24 |
28132400 ps |
| T1238 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1455368394 |
|
|
Jul 24 04:54:55 PM PDT 24 |
Jul 24 04:55:09 PM PDT 24 |
15081200 ps |
| T343 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.497582702 |
|
|
Jul 24 04:55:07 PM PDT 24 |
Jul 24 05:07:51 PM PDT 24 |
3214119200 ps |
| T1239 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3687617935 |
|
|
Jul 24 04:55:00 PM PDT 24 |
Jul 24 04:55:14 PM PDT 24 |
16369500 ps |
| T1240 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3364012923 |
|
|
Jul 24 04:55:10 PM PDT 24 |
Jul 24 04:55:24 PM PDT 24 |
57100600 ps |
| T241 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.594629247 |
|
|
Jul 24 04:54:44 PM PDT 24 |
Jul 24 04:54:57 PM PDT 24 |
21409100 ps |
| T1241 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3526254647 |
|
|
Jul 24 04:54:57 PM PDT 24 |
Jul 24 05:01:27 PM PDT 24 |
509883500 ps |
| T1242 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2299440016 |
|
|
Jul 24 04:55:02 PM PDT 24 |
Jul 24 04:55:19 PM PDT 24 |
42884400 ps |
| T1243 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1998754990 |
|
|
Jul 24 04:55:14 PM PDT 24 |
Jul 24 04:55:28 PM PDT 24 |
49015300 ps |
| T1244 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3594233094 |
|
|
Jul 24 04:55:02 PM PDT 24 |
Jul 24 04:55:18 PM PDT 24 |
14823000 ps |
| T1245 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3161570490 |
|
|
Jul 24 04:55:09 PM PDT 24 |
Jul 24 04:55:23 PM PDT 24 |
71826700 ps |
| T1246 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3057628676 |
|
|
Jul 24 04:54:41 PM PDT 24 |
Jul 24 04:54:54 PM PDT 24 |
12419800 ps |
| T1247 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1559829481 |
|
|
Jul 24 04:54:51 PM PDT 24 |
Jul 24 04:55:09 PM PDT 24 |
71498000 ps |
| T1248 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.73569877 |
|
|
Jul 24 04:55:04 PM PDT 24 |
Jul 24 05:02:49 PM PDT 24 |
321981200 ps |
| T269 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2679789694 |
|
|
Jul 24 04:55:01 PM PDT 24 |
Jul 24 04:55:20 PM PDT 24 |
48498200 ps |
| T1249 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.256020594 |
|
|
Jul 24 04:55:03 PM PDT 24 |
Jul 24 04:55:17 PM PDT 24 |
15099500 ps |
| T1250 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.4082410777 |
|
|
Jul 24 04:54:48 PM PDT 24 |
Jul 24 04:55:06 PM PDT 24 |
59836500 ps |