Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	301639	1		T1	1		T2	1		T3	1
all_values[1]	301639	1		T1	1		T2	1		T3	1
all_values[2]	301639	1		T1	1		T2	1		T3	1
all_values[3]	301639	1		T1	1		T2	1		T3	1
all_values[4]	301639	1		T1	1		T2	1		T3	1
all_values[5]	301639	1		T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	609562	1		T1	6		T2	6		T3	6
auto[1]	1200272	1		T28	2524		T33	13024		T25	6332

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	887779	1		T1	4		T2	4		T3	4
auto[1]	922055	1		T1	2		T2	2		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	301505	1		T1	1		T2	1		T3	1
all_values[0]	auto[1]	auto[1]	134	1		T262	1		T263	1		T334	1
all_values[1]	auto[0]	auto[1]	301484	1		T1	1		T2	1		T3	1
all_values[1]	auto[1]	auto[1]	155	1		T261	2		T262	4		T263	5
all_values[2]	auto[0]	auto[0]	1593	1		T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	62	1		T262	1		T263	2		T334	1
all_values[2]	auto[1]	auto[0]	299932	1		T28	631		T33	3256		T25	1583
all_values[2]	auto[1]	auto[1]	52	1		T262	1		T334	1		T331	3
all_values[3]	auto[0]	auto[0]	1575	1		T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	49	1		T261	1		T262	1		T263	1
all_values[3]	auto[1]	auto[0]	91016	1		T28	294		T33	1628		T25	1583
all_values[3]	auto[1]	auto[1]	208999	1		T28	337		T33	1628		T34	1634
all_values[4]	auto[0]	auto[0]	1140	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	528	1		T8	1		T9	1		T6	1
all_values[4]	auto[1]	auto[0]	191044	1		T28	294		T33	1628		T25	1
all_values[4]	auto[1]	auto[1]	108927	1		T28	337		T33	1628		T25	1582
all_values[5]	auto[0]	auto[0]	1541	1		T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	85	1		T35	1		T36	1		T37	1
all_values[5]	auto[1]	auto[0]	299938	1		T28	631		T33	3256		T25	1583
all_values[5]	auto[1]	auto[1]	75	1		T261	3		T262	2		T263	4