Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	245442	1		T3	5		T4	7		T8	10
auto[FlashEraseBank]	273318	1		T1	2		T3	8		T4	5

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	258374	1		T3	12		T4	11		T8	3
auto[FlashOpProgram]	240180	1		T1	2		T3	1		T4	1
auto[FlashOpErase]	16206	1		T8	5		T5	313		T9	3
auto[FlashOpInvalid]	4000	1		T73	200		T142	200		T119	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	258374	1		T3	12		T4	11		T8	3
op[FlashOpProgram]	240180	1		T1	2		T3	1		T4	1
op[FlashOpErase]	16206	1		T8	5		T5	313		T9	3
read_erase_read	539	1		T20	19		T7	4		T40	11
read_prog_read	782	1		T4	1		T9	1		T6	3

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	375636	1		T1	2		T3	5		T4	5
auto[FlashPartInfo]	138683	1		T3	7		T4	5		T5	1272
auto[FlashPartInfo1]	938	1		T6	1		T23	1		T125	64
auto[FlashPartInfo2]	3503	1		T3	1		T4	2		T6	7

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	187683	1		T3	4		T4	5		T8	3
auto[FlashPartData]	auto[FlashOpProgram]	180394	1		T1	2		T3	1		T8	5
auto[FlashPartData]	auto[FlashOpErase]	3651	1		T8	5		T9	3		T20	3
auto[FlashPartData]	auto[FlashOpInvalid]	3908	1		T73	190		T142	192		T119	198
auto[FlashPartInfo]	auto[FlashOpRead]	67489	1		T3	7		T4	4		T5	646
auto[FlashPartInfo]	auto[FlashOpProgram]	58613	1		T4	1		T5	313		T6	66
auto[FlashPartInfo]	auto[FlashOpErase]	12511	1		T5	313		T20	14		T7	8
auto[FlashPartInfo]	auto[FlashOpInvalid]	70	1		T73	6		T142	4		T119	2
auto[FlashPartInfo1]	auto[FlashOpRead]	759	1		T6	1		T23	1		T125	32
auto[FlashPartInfo1]	auto[FlashOpProgram]	166	1		T125	32		T142	1		T391	1
auto[FlashPartInfo1]	auto[FlashOpErase]	5	1		T142	1		T132	1		T147	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	8	1		T142	2		T147	2		T148	2
auto[FlashPartInfo2]	auto[FlashOpRead]	2443	1		T3	1		T4	2		T6	3
auto[FlashPartInfo2]	auto[FlashOpProgram]	1007	1		T6	4		T23	3		T125	64
auto[FlashPartInfo2]	auto[FlashOpErase]	39	1		T20	2		T40	4		T73	2
auto[FlashPartInfo2]	auto[FlashOpInvalid]	14	1		T73	4		T142	2		T435	4