Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	2	30	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	2	30	93.75	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31516	1		T8	9		T5	600		T88	292
auto[1]	30	1		T317	1		T345	3		T346	4
auto[2]	71	1		T40	4		T74	4		T347	16
auto[3]	216	1		T3	1		T4	1		T20	27

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7956	1		T8	2		T5	150		T20	6
evic_idx[1]	7973	1		T3	1		T4	1		T8	2
evic_idx[2]	7950	1		T8	2		T5	150		T20	8
evic_idx[3]	7954	1		T8	3		T5	150		T20	5

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Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30973	1		T5	600		T20	27		T40	6
evic_op[2]	314	1		T3	1		T4	1		T8	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	2	30	93.75	2

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0] , evic_idx[1]]	[evic_op[2]]	[auto[2]]	--	--	2

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7686	1		T5	150		T88	73		T137	1
evic_idx[0]	evic_op[1]	auto[1]	3	1		T345	1		T346	1		T221	1
evic_idx[0]	evic_op[1]	auto[2]	9	1		T40	1		T74	1		T347	3
evic_idx[0]	evic_op[1]	auto[3]	49	1		T20	6		T74	5		T348	1
evic_idx[0]	evic_op[2]	auto[0]	60	1		T289	4		T215	1		T200	5
evic_idx[0]	evic_op[2]	auto[1]	3	1		T349	1		T350	1		T351	1
evic_idx[0]	evic_op[2]	auto[3]	9	1		T135	1		T38	1		T352	1
evic_idx[1]	evic_op[1]	auto[0]	7686	1		T5	150		T88	73		T137	1
evic_idx[1]	evic_op[1]	auto[1]	7	1		T346	1		T353	1		T354	4
evic_idx[1]	evic_op[1]	auto[2]	12	1		T40	1		T74	1		T347	6
evic_idx[1]	evic_op[1]	auto[3]	45	1		T20	8		T40	1		T74	3
evic_idx[1]	evic_op[2]	auto[0]	67	1		T289	4		T215	1		T200	5
evic_idx[1]	evic_op[2]	auto[1]	1	1		T351	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[3]	18	1		T3	1		T4	1		T56	1
evic_idx[2]	evic_op[1]	auto[0]	7684	1		T5	150		T88	73		T137	1
evic_idx[2]	evic_op[1]	auto[1]	6	1		T345	1		T346	1		T353	1
evic_idx[2]	evic_op[1]	auto[2]	11	1		T40	1		T74	1		T347	4
evic_idx[2]	evic_op[1]	auto[3]	37	1		T20	8		T40	1		T74	3
evic_idx[2]	evic_op[2]	auto[0]	61	1		T289	4		T215	1		T200	5
evic_idx[2]	evic_op[2]	auto[1]	1	1		T355	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[2]	1	1		T356	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[3]	13	1		T24	1		T97	1		T357	1
evic_idx[3]	evic_op[1]	auto[0]	7686	1		T5	150		T88	73		T137	1
evic_idx[3]	evic_op[1]	auto[1]	6	1		T345	1		T346	1		T353	3
evic_idx[3]	evic_op[1]	auto[2]	12	1		T40	1		T74	1		T347	3
evic_idx[3]	evic_op[1]	auto[3]	34	1		T20	5		T74	4		T346	1
evic_idx[3]	evic_op[2]	auto[0]	64	1		T8	1		T240	1		T289	4
evic_idx[3]	evic_op[2]	auto[1]	3	1		T317	1		T358	1		T351	1
evic_idx[3]	evic_op[2]	auto[2]	2	1		T356	1		T359	1		-	-
evic_idx[3]	evic_op[2]	auto[3]	11	1		T134	1		T360	1		T361	1