Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	17604	1		T218	2778		T337	14826		-	-
rd_lvl[2]	17299	1		T218	2248		T247	1286		T117	1404
rd_lvl[3]	25161	1		T218	1167		T338	281		T247	1944
rd_lvl[4]	30746	1		T218	1289		T338	69		T247	353
rd_lvl[5]	10528	1		T218	1189		T247	1372		T117	444
rd_lvl[6]	10331	1		T218	10		T247	534		T339	2520
rd_lvl[7]	10220	1		T218	1158		T247	1041		T339	680
rd_lvl[8]	20679	1		T218	1149		T150	2913		T340	3025
rd_lvl[9]	8750	1		T218	1518		T150	293		T340	319
rd_lvl[10]	7161	1		T33	1137		T218	776		T242	66
rd_lvl[11]	4813	1		T33	491		T238	341		T315	398
rd_lvl[12]	9837	1		T219	1376		T341	1284		T238	502
rd_lvl[13]	2718	1		T34	538		T219	257		T32	231
rd_lvl[14]	11333	1		T34	1096		T31	1234		T32	1555
rd_lvl[15]	2385	1		T28	207		T31	449		T342	106