Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	301639	1		T1	1		T2	1		T3	1
all_pins[1]	301639	1		T1	1		T2	1		T3	1
all_pins[2]	301639	1		T1	1		T2	1		T3	1
all_pins[3]	301639	1		T1	1		T2	1		T3	1
all_pins[4]	301639	1		T1	1		T2	1		T3	1
all_pins[5]	301639	1		T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1499168	1		T1	6		T2	6		T3	6
values[0x1]	310666	1		T28	891		T33	3256		T25	1582
transitions[0x0=>0x1]	282350	1		T28	631		T33	3256		T25	1582
transitions[0x1=>0x0]	282339	1		T28	631		T33	3256		T25	1582

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	301505	1		T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	134	1		T262	1		T263	1		T334	1
all_pins[0]	transitions[0x0=>0x1]	67	1		T262	1		T263	1		T331	2
all_pins[0]	transitions[0x1=>0x0]	88	1		T261	2		T262	4		T263	5
all_pins[1]	values[0x0]	301484	1		T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	155	1		T261	2		T262	4		T263	5
all_pins[1]	transitions[0x0=>0x1]	127	1		T261	2		T262	3		T263	5
all_pins[1]	transitions[0x1=>0x0]	1249	1		T28	130		T342	133		T362	276
all_pins[2]	values[0x0]	300362	1		T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	1277	1		T28	130		T342	133		T362	276
all_pins[2]	transitions[0x0=>0x1]	37	1		T262	1		T331	3		T336	1
all_pins[2]	transitions[0x1=>0x0]	189636	1		T28	207		T33	1628		T34	1634
all_pins[3]	values[0x0]	110763	1		T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	190876	1		T28	337		T33	1628		T34	1634
all_pins[3]	transitions[0x0=>0x1]	163954	1		T28	207		T33	1628		T34	1634
all_pins[3]	transitions[0x1=>0x0]	91227	1		T28	294		T33	1628		T25	1582
all_pins[4]	values[0x0]	183490	1		T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	118149	1		T28	424		T33	1628		T25	1582
all_pins[4]	transitions[0x0=>0x1]	118128	1		T28	424		T33	1628		T25	1582
all_pins[4]	transitions[0x1=>0x0]	54	1		T261	3		T262	2		T263	2
all_pins[5]	values[0x0]	301564	1		T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	75	1		T261	3		T262	2		T263	4
all_pins[5]	transitions[0x0=>0x1]	37	1		T261	3		T263	3		T334	2
all_pins[5]	transitions[0x1=>0x0]	85	1		T334	1		T331	2		T332	3