| T1070 |
/workspace/coverage/default/0.flash_ctrl_connect.3789412748 |
|
|
Jul 26 07:25:40 PM PDT 24 |
Jul 26 07:25:56 PM PDT 24 |
59904500 ps |
| T1071 |
/workspace/coverage/default/30.flash_ctrl_connect.1891686578 |
|
|
Jul 26 07:32:26 PM PDT 24 |
Jul 26 07:32:39 PM PDT 24 |
39744000 ps |
| T1072 |
/workspace/coverage/default/38.flash_ctrl_sec_info_access.714580606 |
|
|
Jul 26 07:32:49 PM PDT 24 |
Jul 26 07:33:53 PM PDT 24 |
1140598000 ps |
| T1073 |
/workspace/coverage/default/69.flash_ctrl_otp_reset.1275951824 |
|
|
Jul 26 07:33:47 PM PDT 24 |
Jul 26 07:35:37 PM PDT 24 |
38570700 ps |
| T210 |
/workspace/coverage/default/2.flash_ctrl_derr_detect.3564453646 |
|
|
Jul 26 07:25:59 PM PDT 24 |
Jul 26 07:28:59 PM PDT 24 |
2921041800 ps |
| T44 |
/workspace/coverage/default/0.flash_ctrl_access_after_disable.1681815408 |
|
|
Jul 26 07:25:39 PM PDT 24 |
Jul 26 07:25:53 PM PDT 24 |
188389300 ps |
| T1074 |
/workspace/coverage/default/26.flash_ctrl_connect.135560336 |
|
|
Jul 26 07:32:03 PM PDT 24 |
Jul 26 07:32:19 PM PDT 24 |
148301200 ps |
| T1075 |
/workspace/coverage/default/56.flash_ctrl_otp_reset.3388962319 |
|
|
Jul 26 07:33:52 PM PDT 24 |
Jul 26 07:36:05 PM PDT 24 |
192990000 ps |
| T1076 |
/workspace/coverage/default/0.flash_ctrl_error_mp.3166287684 |
|
|
Jul 26 07:25:30 PM PDT 24 |
Jul 26 08:04:47 PM PDT 24 |
2376205400 ps |
| T1077 |
/workspace/coverage/default/18.flash_ctrl_rand_ops.3472305555 |
|
|
Jul 26 07:31:14 PM PDT 24 |
Jul 26 07:53:39 PM PDT 24 |
2562320900 ps |
| T374 |
/workspace/coverage/default/41.flash_ctrl_disable.1033102753 |
|
|
Jul 26 07:33:07 PM PDT 24 |
Jul 26 07:33:30 PM PDT 24 |
26579300 ps |
| T1078 |
/workspace/coverage/default/26.flash_ctrl_intr_rd.3993761658 |
|
|
Jul 26 07:31:49 PM PDT 24 |
Jul 26 07:33:43 PM PDT 24 |
930410700 ps |
| T1079 |
/workspace/coverage/default/0.flash_ctrl_full_mem_access.3492492958 |
|
|
Jul 26 07:25:33 PM PDT 24 |
Jul 26 08:25:51 PM PDT 24 |
1165323030100 ps |
| T231 |
/workspace/coverage/default/4.flash_ctrl_ro_derr.1191728152 |
|
|
Jul 26 07:27:18 PM PDT 24 |
Jul 26 07:29:51 PM PDT 24 |
1213812300 ps |
| T1080 |
/workspace/coverage/default/4.flash_ctrl_smoke.2228231926 |
|
|
Jul 26 07:26:27 PM PDT 24 |
Jul 26 07:29:16 PM PDT 24 |
39772400 ps |
| T1081 |
/workspace/coverage/default/29.flash_ctrl_sec_info_access.2622434536 |
|
|
Jul 26 07:32:15 PM PDT 24 |
Jul 26 07:33:12 PM PDT 24 |
935639600 ps |
| T1082 |
/workspace/coverage/default/39.flash_ctrl_disable.874541052 |
|
|
Jul 26 07:32:59 PM PDT 24 |
Jul 26 07:33:21 PM PDT 24 |
12671100 ps |
| T1083 |
/workspace/coverage/default/6.flash_ctrl_hw_rma_reset.3900742385 |
|
|
Jul 26 07:27:39 PM PDT 24 |
Jul 26 07:45:08 PM PDT 24 |
160186019500 ps |
| T1084 |
/workspace/coverage/default/14.flash_ctrl_lcmgr_intg.2962229280 |
|
|
Jul 26 07:30:59 PM PDT 24 |
Jul 26 07:31:13 PM PDT 24 |
29728500 ps |
| T1085 |
/workspace/coverage/default/13.flash_ctrl_hw_sec_otp.270287281 |
|
|
Jul 26 07:30:47 PM PDT 24 |
Jul 26 07:32:09 PM PDT 24 |
2387905300 ps |
| T1086 |
/workspace/coverage/default/44.flash_ctrl_connect.3597403090 |
|
|
Jul 26 07:33:13 PM PDT 24 |
Jul 26 07:33:26 PM PDT 24 |
16461400 ps |
| T1087 |
/workspace/coverage/default/27.flash_ctrl_hw_sec_otp.4043398210 |
|
|
Jul 26 07:32:09 PM PDT 24 |
Jul 26 07:33:41 PM PDT 24 |
4101588500 ps |
| T1088 |
/workspace/coverage/default/10.flash_ctrl_smoke.1421135729 |
|
|
Jul 26 07:28:46 PM PDT 24 |
Jul 26 07:30:48 PM PDT 24 |
63473000 ps |
| T1089 |
/workspace/coverage/default/11.flash_ctrl_prog_reset.2706972284 |
|
|
Jul 26 07:28:57 PM PDT 24 |
Jul 26 07:29:12 PM PDT 24 |
43247100 ps |
| T1090 |
/workspace/coverage/default/34.flash_ctrl_hw_sec_otp.572946264 |
|
|
Jul 26 07:32:35 PM PDT 24 |
Jul 26 07:34:10 PM PDT 24 |
3267155500 ps |
| T1091 |
/workspace/coverage/default/7.flash_ctrl_disable.2724216768 |
|
|
Jul 26 07:27:57 PM PDT 24 |
Jul 26 07:28:19 PM PDT 24 |
11106700 ps |
| T1092 |
/workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.3952895189 |
|
|
Jul 26 07:25:59 PM PDT 24 |
Jul 26 07:26:22 PM PDT 24 |
32365800 ps |
| T1093 |
/workspace/coverage/default/13.flash_ctrl_mp_regions.2335933076 |
|
|
Jul 26 07:30:46 PM PDT 24 |
Jul 26 07:43:12 PM PDT 24 |
9033367700 ps |
| T1094 |
/workspace/coverage/default/25.flash_ctrl_disable.4167954962 |
|
|
Jul 26 07:31:50 PM PDT 24 |
Jul 26 07:32:12 PM PDT 24 |
34799700 ps |
| T1095 |
/workspace/coverage/default/3.flash_ctrl_rand_ops.2812218172 |
|
|
Jul 26 07:26:11 PM PDT 24 |
Jul 26 07:35:51 PM PDT 24 |
1703628800 ps |
| T434 |
/workspace/coverage/default/6.flash_ctrl_ro_derr.3546879797 |
|
|
Jul 26 07:27:41 PM PDT 24 |
Jul 26 07:30:17 PM PDT 24 |
1286113100 ps |
| T1096 |
/workspace/coverage/default/26.flash_ctrl_rw_evict.3141895801 |
|
|
Jul 26 07:31:51 PM PDT 24 |
Jul 26 07:32:22 PM PDT 24 |
81484100 ps |
| T1097 |
/workspace/coverage/default/7.flash_ctrl_invalid_op.3389209626 |
|
|
Jul 26 07:27:49 PM PDT 24 |
Jul 26 07:29:04 PM PDT 24 |
999603500 ps |
| T1098 |
/workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.853101778 |
|
|
Jul 26 07:32:27 PM PDT 24 |
Jul 26 07:32:58 PM PDT 24 |
28441100 ps |
| T1099 |
/workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.2522955994 |
|
|
Jul 26 07:32:15 PM PDT 24 |
Jul 26 07:32:46 PM PDT 24 |
40049700 ps |
| T1100 |
/workspace/coverage/default/9.flash_ctrl_prog_reset.4000134903 |
|
|
Jul 26 07:28:43 PM PDT 24 |
Jul 26 07:32:16 PM PDT 24 |
2530036400 ps |
| T1101 |
/workspace/coverage/default/5.flash_ctrl_rw_evict.26258580 |
|
|
Jul 26 07:27:39 PM PDT 24 |
Jul 26 07:28:10 PM PDT 24 |
42675500 ps |
| T1102 |
/workspace/coverage/default/29.flash_ctrl_rw_evict.3408380950 |
|
|
Jul 26 07:32:16 PM PDT 24 |
Jul 26 07:32:47 PM PDT 24 |
59928000 ps |
| T1103 |
/workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.2821105465 |
|
|
Jul 26 07:27:52 PM PDT 24 |
Jul 26 07:28:06 PM PDT 24 |
16099700 ps |
| T1104 |
/workspace/coverage/default/1.flash_ctrl_oversize_error.3149850764 |
|
|
Jul 26 07:25:49 PM PDT 24 |
Jul 26 07:28:52 PM PDT 24 |
4743196800 ps |
| T1105 |
/workspace/coverage/default/1.flash_ctrl_rw_evict.257081891 |
|
|
Jul 26 07:25:50 PM PDT 24 |
Jul 26 07:26:21 PM PDT 24 |
86845900 ps |
| T1106 |
/workspace/coverage/default/10.flash_ctrl_invalid_op.946428417 |
|
|
Jul 26 07:28:43 PM PDT 24 |
Jul 26 07:29:55 PM PDT 24 |
10950749500 ps |
| T1107 |
/workspace/coverage/default/48.flash_ctrl_alert_test.2398750143 |
|
|
Jul 26 07:33:33 PM PDT 24 |
Jul 26 07:33:47 PM PDT 24 |
456238000 ps |
| T1108 |
/workspace/coverage/default/4.flash_ctrl_ro_serr.2296103112 |
|
|
Jul 26 07:27:24 PM PDT 24 |
Jul 26 07:29:55 PM PDT 24 |
2391769100 ps |
| T1109 |
/workspace/coverage/default/34.flash_ctrl_rw_evict.3540478598 |
|
|
Jul 26 07:32:33 PM PDT 24 |
Jul 26 07:33:03 PM PDT 24 |
56058300 ps |
| T1110 |
/workspace/coverage/default/46.flash_ctrl_alert_test.3292207265 |
|
|
Jul 26 07:33:22 PM PDT 24 |
Jul 26 07:33:36 PM PDT 24 |
55299900 ps |
| T1111 |
/workspace/coverage/default/5.flash_ctrl_rw.367561346 |
|
|
Jul 26 07:27:38 PM PDT 24 |
Jul 26 07:36:31 PM PDT 24 |
3989657100 ps |
| T1112 |
/workspace/coverage/default/13.flash_ctrl_disable.1169183320 |
|
|
Jul 26 07:30:49 PM PDT 24 |
Jul 26 07:31:09 PM PDT 24 |
49080600 ps |
| T1113 |
/workspace/coverage/default/65.flash_ctrl_connect.2062010077 |
|
|
Jul 26 07:33:49 PM PDT 24 |
Jul 26 07:34:05 PM PDT 24 |
15659700 ps |
| T16 |
/workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.1734054561 |
|
|
Jul 26 07:25:39 PM PDT 24 |
Jul 26 07:25:54 PM PDT 24 |
14832700 ps |
| T1114 |
/workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.194638917 |
|
|
Jul 26 07:27:42 PM PDT 24 |
Jul 26 07:30:47 PM PDT 24 |
79721990400 ps |
| T1115 |
/workspace/coverage/default/3.flash_ctrl_rw_evict.3717675897 |
|
|
Jul 26 07:26:20 PM PDT 24 |
Jul 26 07:26:50 PM PDT 24 |
26725600 ps |
| T1116 |
/workspace/coverage/default/60.flash_ctrl_otp_reset.181126143 |
|
|
Jul 26 07:33:49 PM PDT 24 |
Jul 26 07:35:42 PM PDT 24 |
39819400 ps |
| T1117 |
/workspace/coverage/default/14.flash_ctrl_intr_rd.2838300282 |
|
|
Jul 26 07:30:59 PM PDT 24 |
Jul 26 07:32:53 PM PDT 24 |
1094291400 ps |
| T1118 |
/workspace/coverage/default/42.flash_ctrl_disable.954330908 |
|
|
Jul 26 07:33:11 PM PDT 24 |
Jul 26 07:33:32 PM PDT 24 |
13484600 ps |
| T1119 |
/workspace/coverage/default/25.flash_ctrl_rw_evict.1927847077 |
|
|
Jul 26 07:31:51 PM PDT 24 |
Jul 26 07:32:22 PM PDT 24 |
79651700 ps |
| T1120 |
/workspace/coverage/default/20.flash_ctrl_sec_info_access.2770938302 |
|
|
Jul 26 07:31:25 PM PDT 24 |
Jul 26 07:32:35 PM PDT 24 |
2043434200 ps |
| T1121 |
/workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.937105799 |
|
|
Jul 26 07:27:38 PM PDT 24 |
Jul 26 07:33:11 PM PDT 24 |
34961494100 ps |
| T61 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3338741654 |
|
|
Jul 26 07:20:07 PM PDT 24 |
Jul 26 07:20:24 PM PDT 24 |
59843600 ps |
| T62 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1934015073 |
|
|
Jul 26 07:18:53 PM PDT 24 |
Jul 26 07:19:08 PM PDT 24 |
71602000 ps |
| T1122 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1742299445 |
|
|
Jul 26 07:20:18 PM PDT 24 |
Jul 26 07:20:34 PM PDT 24 |
26295700 ps |
| T63 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2562707041 |
|
|
Jul 26 07:18:44 PM PDT 24 |
Jul 26 07:19:17 PM PDT 24 |
59097700 ps |
| T100 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2538839611 |
|
|
Jul 26 07:19:18 PM PDT 24 |
Jul 26 07:20:44 PM PDT 24 |
3101392300 ps |
| T256 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.440010289 |
|
|
Jul 26 07:20:21 PM PDT 24 |
Jul 26 07:20:42 PM PDT 24 |
321150800 ps |
| T261 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.1719116699 |
|
|
Jul 26 07:19:18 PM PDT 24 |
Jul 26 07:19:32 PM PDT 24 |
33038600 ps |
| T103 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1920246494 |
|
|
Jul 26 07:19:23 PM PDT 24 |
Jul 26 07:19:42 PM PDT 24 |
90602700 ps |
| T1123 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1492627585 |
|
|
Jul 26 07:19:24 PM PDT 24 |
Jul 26 07:19:37 PM PDT 24 |
49638500 ps |
| T230 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2441754921 |
|
|
Jul 26 07:19:56 PM PDT 24 |
Jul 26 07:20:14 PM PDT 24 |
86387300 ps |
| T277 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1783382036 |
|
|
Jul 26 07:19:10 PM PDT 24 |
Jul 26 07:19:24 PM PDT 24 |
17607600 ps |
| T257 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3176296220 |
|
|
Jul 26 07:20:06 PM PDT 24 |
Jul 26 07:20:41 PM PDT 24 |
547999900 ps |
| T282 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.696763579 |
|
|
Jul 26 07:19:50 PM PDT 24 |
Jul 26 07:20:08 PM PDT 24 |
48594300 ps |
| T104 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2227021628 |
|
|
Jul 26 07:20:28 PM PDT 24 |
Jul 26 07:20:47 PM PDT 24 |
63529500 ps |
| T262 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2154166771 |
|
|
Jul 26 07:18:26 PM PDT 24 |
Jul 26 07:18:39 PM PDT 24 |
51198400 ps |
| T263 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.1812740126 |
|
|
Jul 26 07:20:49 PM PDT 24 |
Jul 26 07:21:03 PM PDT 24 |
36976600 ps |
| T334 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1154891365 |
|
|
Jul 26 07:19:42 PM PDT 24 |
Jul 26 07:19:56 PM PDT 24 |
20934800 ps |
| T1124 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.2593941912 |
|
|
Jul 26 07:19:43 PM PDT 24 |
Jul 26 07:19:59 PM PDT 24 |
20282600 ps |
| T229 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.4131371667 |
|
|
Jul 26 07:20:11 PM PDT 24 |
Jul 26 07:20:31 PM PDT 24 |
122821400 ps |
| T101 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1374530509 |
|
|
Jul 26 07:19:51 PM PDT 24 |
Jul 26 07:27:27 PM PDT 24 |
357179000 ps |
| T283 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1249747147 |
|
|
Jul 26 07:18:51 PM PDT 24 |
Jul 26 07:19:48 PM PDT 24 |
1575470900 ps |
| T102 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.29374393 |
|
|
Jul 26 07:19:09 PM PDT 24 |
Jul 26 07:25:38 PM PDT 24 |
498957200 ps |
| T331 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.1426239581 |
|
|
Jul 26 07:20:48 PM PDT 24 |
Jul 26 07:21:02 PM PDT 24 |
90663000 ps |
| T332 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.115561687 |
|
|
Jul 26 07:20:38 PM PDT 24 |
Jul 26 07:20:51 PM PDT 24 |
39629100 ps |
| T1125 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2926586052 |
|
|
Jul 26 07:19:56 PM PDT 24 |
Jul 26 07:20:12 PM PDT 24 |
15078400 ps |
| T1126 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1424058423 |
|
|
Jul 26 07:19:42 PM PDT 24 |
Jul 26 07:19:58 PM PDT 24 |
12245100 ps |
| T1127 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.32018002 |
|
|
Jul 26 07:19:51 PM PDT 24 |
Jul 26 07:20:04 PM PDT 24 |
11726700 ps |
| T1128 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1089345189 |
|
|
Jul 26 07:19:17 PM PDT 24 |
Jul 26 07:19:33 PM PDT 24 |
13690500 ps |
| T255 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1271064707 |
|
|
Jul 26 07:20:14 PM PDT 24 |
Jul 26 07:27:53 PM PDT 24 |
199110900 ps |
| T304 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.4182154410 |
|
|
Jul 26 07:18:36 PM PDT 24 |
Jul 26 07:19:13 PM PDT 24 |
1364332600 ps |
| T274 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1418712356 |
|
|
Jul 26 07:19:43 PM PDT 24 |
Jul 26 07:27:16 PM PDT 24 |
656139300 ps |
| T1129 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.808179166 |
|
|
Jul 26 07:18:52 PM PDT 24 |
Jul 26 07:20:14 PM PDT 24 |
19201370500 ps |
| T284 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1254069861 |
|
|
Jul 26 07:20:12 PM PDT 24 |
Jul 26 07:20:28 PM PDT 24 |
295272800 ps |
| T285 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.4003240705 |
|
|
Jul 26 07:19:43 PM PDT 24 |
Jul 26 07:20:17 PM PDT 24 |
462173300 ps |
| T266 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1103809449 |
|
|
Jul 26 07:19:17 PM PDT 24 |
Jul 26 07:19:34 PM PDT 24 |
147182600 ps |
| T1130 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3574559661 |
|
|
Jul 26 07:19:00 PM PDT 24 |
Jul 26 07:19:37 PM PDT 24 |
336001100 ps |
| T267 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.480060680 |
|
|
Jul 26 07:19:02 PM PDT 24 |
Jul 26 07:19:33 PM PDT 24 |
20138000 ps |
| T1131 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1630529360 |
|
|
Jul 26 07:18:34 PM PDT 24 |
Jul 26 07:18:50 PM PDT 24 |
43836800 ps |
| T333 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2612488961 |
|
|
Jul 26 07:18:52 PM PDT 24 |
Jul 26 07:19:06 PM PDT 24 |
83908700 ps |
| T1132 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.4063852748 |
|
|
Jul 26 07:19:51 PM PDT 24 |
Jul 26 07:20:04 PM PDT 24 |
22720900 ps |
| T268 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.4080350778 |
|
|
Jul 26 07:20:11 PM PDT 24 |
Jul 26 07:26:45 PM PDT 24 |
804216500 ps |
| T1133 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2354694901 |
|
|
Jul 26 07:18:24 PM PDT 24 |
Jul 26 07:18:38 PM PDT 24 |
15417800 ps |
| T1134 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2924285272 |
|
|
Jul 26 07:20:15 PM PDT 24 |
Jul 26 07:20:31 PM PDT 24 |
116143500 ps |
| T305 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.655464032 |
|
|
Jul 26 07:19:10 PM PDT 24 |
Jul 26 07:19:36 PM PDT 24 |
583170100 ps |
| T278 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2060576779 |
|
|
Jul 26 07:18:25 PM PDT 24 |
Jul 26 07:18:39 PM PDT 24 |
46551100 ps |
| T336 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.1368717875 |
|
|
Jul 26 07:20:48 PM PDT 24 |
Jul 26 07:21:01 PM PDT 24 |
50478000 ps |
| T1135 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.268404173 |
|
|
Jul 26 07:20:05 PM PDT 24 |
Jul 26 07:20:21 PM PDT 24 |
66664900 ps |
| T1136 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1629783594 |
|
|
Jul 26 07:18:54 PM PDT 24 |
Jul 26 07:19:10 PM PDT 24 |
280832700 ps |
| T272 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.567162856 |
|
|
Jul 26 07:19:49 PM PDT 24 |
Jul 26 07:34:57 PM PDT 24 |
824293800 ps |
| T259 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.379396685 |
|
|
Jul 26 07:20:07 PM PDT 24 |
Jul 26 07:20:23 PM PDT 24 |
104598300 ps |
| T306 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3409977051 |
|
|
Jul 26 07:19:56 PM PDT 24 |
Jul 26 07:20:32 PM PDT 24 |
431103100 ps |
| T307 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2731567324 |
|
|
Jul 26 07:20:31 PM PDT 24 |
Jul 26 07:20:48 PM PDT 24 |
48562300 ps |
| T260 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1178929769 |
|
|
Jul 26 07:20:10 PM PDT 24 |
Jul 26 07:20:27 PM PDT 24 |
72894300 ps |
| T275 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2078785187 |
|
|
Jul 26 07:20:19 PM PDT 24 |
Jul 26 07:20:37 PM PDT 24 |
27620500 ps |
| T308 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2081181491 |
|
|
Jul 26 07:19:16 PM PDT 24 |
Jul 26 07:19:32 PM PDT 24 |
209999300 ps |
| T1137 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.861740043 |
|
|
Jul 26 07:20:48 PM PDT 24 |
Jul 26 07:21:02 PM PDT 24 |
23472200 ps |
| T258 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.382810636 |
|
|
Jul 26 07:18:53 PM PDT 24 |
Jul 26 07:19:11 PM PDT 24 |
53946100 ps |
| T1138 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.792994618 |
|
|
Jul 26 07:19:21 PM PDT 24 |
Jul 26 07:19:38 PM PDT 24 |
196117600 ps |
| T335 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2041869669 |
|
|
Jul 26 07:19:59 PM PDT 24 |
Jul 26 07:20:12 PM PDT 24 |
15795500 ps |
| T1139 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2140433356 |
|
|
Jul 26 07:20:38 PM PDT 24 |
Jul 26 07:20:52 PM PDT 24 |
30146300 ps |
| T309 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.881612178 |
|
|
Jul 26 07:18:37 PM PDT 24 |
Jul 26 07:18:56 PM PDT 24 |
99817700 ps |
| T310 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1986623901 |
|
|
Jul 26 07:18:52 PM PDT 24 |
Jul 26 07:19:10 PM PDT 24 |
238149500 ps |
| T1140 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.685996231 |
|
|
Jul 26 07:19:33 PM PDT 24 |
Jul 26 07:19:47 PM PDT 24 |
163147800 ps |
| T1141 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1462196450 |
|
|
Jul 26 07:20:47 PM PDT 24 |
Jul 26 07:21:01 PM PDT 24 |
29188300 ps |
| T1142 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2700859912 |
|
|
Jul 26 07:19:58 PM PDT 24 |
Jul 26 07:20:12 PM PDT 24 |
72268200 ps |
| T1143 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1935740869 |
|
|
Jul 26 07:20:26 PM PDT 24 |
Jul 26 07:20:40 PM PDT 24 |
52158500 ps |
| T1144 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1501994408 |
|
|
Jul 26 07:20:21 PM PDT 24 |
Jul 26 07:20:36 PM PDT 24 |
14155500 ps |
| T1145 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2351621060 |
|
|
Jul 26 07:19:49 PM PDT 24 |
Jul 26 07:20:07 PM PDT 24 |
258995800 ps |
| T1146 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3596659307 |
|
|
Jul 26 07:19:10 PM PDT 24 |
Jul 26 07:19:24 PM PDT 24 |
30636400 ps |
| T1147 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1590167120 |
|
|
Jul 26 07:20:29 PM PDT 24 |
Jul 26 07:20:46 PM PDT 24 |
88819600 ps |
| T264 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.319302802 |
|
|
Jul 26 07:20:22 PM PDT 24 |
Jul 26 07:20:39 PM PDT 24 |
46005000 ps |
| T364 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3463048329 |
|
|
Jul 26 07:20:04 PM PDT 24 |
Jul 26 07:35:09 PM PDT 24 |
2650668900 ps |
| T311 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3242890634 |
|
|
Jul 26 07:19:41 PM PDT 24 |
Jul 26 07:19:58 PM PDT 24 |
62745000 ps |
| T363 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.208836021 |
|
|
Jul 26 07:20:20 PM PDT 24 |
Jul 26 07:35:42 PM PDT 24 |
2857752300 ps |
| T1148 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3041218861 |
|
|
Jul 26 07:20:04 PM PDT 24 |
Jul 26 07:20:22 PM PDT 24 |
553637400 ps |
| T265 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3927659600 |
|
|
Jul 26 07:19:00 PM PDT 24 |
Jul 26 07:34:06 PM PDT 24 |
776944100 ps |
| T1149 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2813450094 |
|
|
Jul 26 07:18:35 PM PDT 24 |
Jul 26 07:19:39 PM PDT 24 |
2635903700 ps |
| T1150 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3900010886 |
|
|
Jul 26 07:19:32 PM PDT 24 |
Jul 26 07:19:46 PM PDT 24 |
46968600 ps |
| T1151 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.236220915 |
|
|
Jul 26 07:19:00 PM PDT 24 |
Jul 26 07:19:16 PM PDT 24 |
37473000 ps |
| T1152 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2701825159 |
|
|
Jul 26 07:20:20 PM PDT 24 |
Jul 26 07:27:02 PM PDT 24 |
1689500500 ps |
| T269 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1384383928 |
|
|
Jul 26 07:18:59 PM PDT 24 |
Jul 26 07:19:18 PM PDT 24 |
54339800 ps |
| T1153 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1509674464 |
|
|
Jul 26 07:18:43 PM PDT 24 |
Jul 26 07:19:17 PM PDT 24 |
229571700 ps |
| T1154 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1575251693 |
|
|
Jul 26 07:19:15 PM PDT 24 |
Jul 26 07:19:29 PM PDT 24 |
44987900 ps |
| T1155 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3165290556 |
|
|
Jul 26 07:19:43 PM PDT 24 |
Jul 26 07:19:57 PM PDT 24 |
42570700 ps |
| T1156 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2992834915 |
|
|
Jul 26 07:18:26 PM PDT 24 |
Jul 26 07:18:42 PM PDT 24 |
22353800 ps |
| T1157 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2341614475 |
|
|
Jul 26 07:20:37 PM PDT 24 |
Jul 26 07:20:50 PM PDT 24 |
46799800 ps |
| T1158 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1739581840 |
|
|
Jul 26 07:19:49 PM PDT 24 |
Jul 26 07:20:02 PM PDT 24 |
147760900 ps |
| T1159 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1789230206 |
|
|
Jul 26 07:19:33 PM PDT 24 |
Jul 26 07:19:48 PM PDT 24 |
35004300 ps |
| T1160 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1982621131 |
|
|
Jul 26 07:20:19 PM PDT 24 |
Jul 26 07:20:35 PM PDT 24 |
13592100 ps |
| T1161 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.3843498532 |
|
|
Jul 26 07:20:08 PM PDT 24 |
Jul 26 07:20:26 PM PDT 24 |
344164800 ps |
| T1162 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2979790366 |
|
|
Jul 26 07:20:04 PM PDT 24 |
Jul 26 07:20:20 PM PDT 24 |
363214700 ps |
| T1163 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2855111208 |
|
|
Jul 26 07:20:38 PM PDT 24 |
Jul 26 07:20:52 PM PDT 24 |
46327100 ps |
| T1164 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3111265869 |
|
|
Jul 26 07:19:51 PM PDT 24 |
Jul 26 07:20:04 PM PDT 24 |
27860900 ps |
| T1165 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2704943923 |
|
|
Jul 26 07:20:35 PM PDT 24 |
Jul 26 07:20:49 PM PDT 24 |
119623500 ps |
| T1166 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.4106934214 |
|
|
Jul 26 07:20:38 PM PDT 24 |
Jul 26 07:20:51 PM PDT 24 |
42934500 ps |
| T1167 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2237658766 |
|
|
Jul 26 07:19:56 PM PDT 24 |
Jul 26 07:20:10 PM PDT 24 |
28013800 ps |
| T270 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1360297911 |
|
|
Jul 26 07:19:49 PM PDT 24 |
Jul 26 07:20:05 PM PDT 24 |
194712700 ps |
| T1168 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2299688222 |
|
|
Jul 26 07:19:50 PM PDT 24 |
Jul 26 07:20:04 PM PDT 24 |
27390400 ps |
| T1169 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1533372398 |
|
|
Jul 26 07:19:33 PM PDT 24 |
Jul 26 07:20:03 PM PDT 24 |
652632900 ps |
| T1170 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2004026855 |
|
|
Jul 26 07:20:03 PM PDT 24 |
Jul 26 07:20:16 PM PDT 24 |
51300800 ps |
| T370 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3616376522 |
|
|
Jul 26 07:19:31 PM PDT 24 |
Jul 26 07:34:56 PM PDT 24 |
5342752400 ps |
| T273 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.873308165 |
|
|
Jul 26 07:20:20 PM PDT 24 |
Jul 26 07:20:36 PM PDT 24 |
38006800 ps |
| T1171 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3379830728 |
|
|
Jul 26 07:20:04 PM PDT 24 |
Jul 26 07:20:18 PM PDT 24 |
52235300 ps |
| T1172 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1376532087 |
|
|
Jul 26 07:20:10 PM PDT 24 |
Jul 26 07:20:28 PM PDT 24 |
165558900 ps |
| T1173 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1198191113 |
|
|
Jul 26 07:19:41 PM PDT 24 |
Jul 26 07:19:58 PM PDT 24 |
52745200 ps |
| T1174 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.68614399 |
|
|
Jul 26 07:20:11 PM PDT 24 |
Jul 26 07:20:24 PM PDT 24 |
45731500 ps |
| T1175 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2826487475 |
|
|
Jul 26 07:20:04 PM PDT 24 |
Jul 26 07:20:20 PM PDT 24 |
17888600 ps |
| T1176 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3472311749 |
|
|
Jul 26 07:20:21 PM PDT 24 |
Jul 26 07:20:39 PM PDT 24 |
469041200 ps |
| T1177 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2047319108 |
|
|
Jul 26 07:19:32 PM PDT 24 |
Jul 26 07:19:51 PM PDT 24 |
418122700 ps |
| T1178 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.4097505819 |
|
|
Jul 26 07:18:43 PM PDT 24 |
Jul 26 07:19:00 PM PDT 24 |
934286400 ps |
| T1179 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3923927250 |
|
|
Jul 26 07:19:09 PM PDT 24 |
Jul 26 07:19:22 PM PDT 24 |
30037800 ps |
| T1180 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.50997709 |
|
|
Jul 26 07:20:37 PM PDT 24 |
Jul 26 07:20:51 PM PDT 24 |
26060500 ps |
| T1181 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1894834593 |
|
|
Jul 26 07:19:01 PM PDT 24 |
Jul 26 07:19:16 PM PDT 24 |
43890200 ps |
| T1182 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1356436906 |
|
|
Jul 26 07:20:02 PM PDT 24 |
Jul 26 07:20:16 PM PDT 24 |
13187300 ps |
| T1183 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2794408180 |
|
|
Jul 26 07:20:22 PM PDT 24 |
Jul 26 07:20:43 PM PDT 24 |
1058420600 ps |
| T369 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.744173726 |
|
|
Jul 26 07:18:26 PM PDT 24 |
Jul 26 07:26:05 PM PDT 24 |
781364200 ps |
| T1184 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.593980554 |
|
|
Jul 26 07:19:15 PM PDT 24 |
Jul 26 07:25:47 PM PDT 24 |
521918300 ps |
| T1185 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2280203278 |
|
|
Jul 26 07:19:23 PM PDT 24 |
Jul 26 07:19:41 PM PDT 24 |
988054300 ps |
| T1186 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2223724330 |
|
|
Jul 26 07:20:37 PM PDT 24 |
Jul 26 07:20:51 PM PDT 24 |
15493500 ps |
| T1187 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.4114779205 |
|
|
Jul 26 07:20:29 PM PDT 24 |
Jul 26 07:20:44 PM PDT 24 |
17118700 ps |
| T1188 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2494054817 |
|
|
Jul 26 07:18:53 PM PDT 24 |
Jul 26 07:19:09 PM PDT 24 |
14873200 ps |
| T1189 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3470526166 |
|
|
Jul 26 07:20:20 PM PDT 24 |
Jul 26 07:20:34 PM PDT 24 |
37663600 ps |
| T271 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.1340835746 |
|
|
Jul 26 07:18:43 PM PDT 24 |
Jul 26 07:19:04 PM PDT 24 |
247760700 ps |
| T1190 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.3406609322 |
|
|
Jul 26 07:20:37 PM PDT 24 |
Jul 26 07:20:51 PM PDT 24 |
19949600 ps |
| T1191 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2350828837 |
|
|
Jul 26 07:20:48 PM PDT 24 |
Jul 26 07:21:02 PM PDT 24 |
26313900 ps |
| T1192 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.560123123 |
|
|
Jul 26 07:20:20 PM PDT 24 |
Jul 26 07:20:33 PM PDT 24 |
28058100 ps |
| T1193 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.667600645 |
|
|
Jul 26 07:19:51 PM PDT 24 |
Jul 26 07:20:26 PM PDT 24 |
346164300 ps |
| T1194 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3080065877 |
|
|
Jul 26 07:19:01 PM PDT 24 |
Jul 26 07:19:14 PM PDT 24 |
15610700 ps |
| T1195 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2677892664 |
|
|
Jul 26 07:20:31 PM PDT 24 |
Jul 26 07:20:45 PM PDT 24 |
29314800 ps |
| T1196 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1065825238 |
|
|
Jul 26 07:18:51 PM PDT 24 |
Jul 26 07:19:08 PM PDT 24 |
20742500 ps |
| T1197 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1430637599 |
|
|
Jul 26 07:19:33 PM PDT 24 |
Jul 26 07:19:50 PM PDT 24 |
29827600 ps |
| T1198 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1636884358 |
|
|
Jul 26 07:18:43 PM PDT 24 |
Jul 26 07:20:02 PM PDT 24 |
10965534300 ps |
| T1199 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1029981124 |
|
|
Jul 26 07:19:31 PM PDT 24 |
Jul 26 07:19:45 PM PDT 24 |
20656600 ps |
| T365 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1790104240 |
|
|
Jul 26 07:19:42 PM PDT 24 |
Jul 26 07:27:12 PM PDT 24 |
686568000 ps |
| T1200 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.1457114836 |
|
|
Jul 26 07:20:50 PM PDT 24 |
Jul 26 07:21:04 PM PDT 24 |
16278700 ps |
| T1201 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.4250710752 |
|
|
Jul 26 07:19:56 PM PDT 24 |
Jul 26 07:20:12 PM PDT 24 |
37301900 ps |
| T1202 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1982579936 |
|
|
Jul 26 07:18:43 PM PDT 24 |
Jul 26 07:18:57 PM PDT 24 |
44047500 ps |
| T1203 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.949236096 |
|
|
Jul 26 07:20:11 PM PDT 24 |
Jul 26 07:20:27 PM PDT 24 |
45117100 ps |
| T279 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2384427964 |
|
|
Jul 26 07:18:54 PM PDT 24 |
Jul 26 07:19:08 PM PDT 24 |
23750100 ps |
| T1204 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3474454027 |
|
|
Jul 26 07:19:57 PM PDT 24 |
Jul 26 07:20:11 PM PDT 24 |
125069400 ps |
| T1205 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3415488462 |
|
|
Jul 26 07:19:57 PM PDT 24 |
Jul 26 07:20:32 PM PDT 24 |
807513100 ps |
| T1206 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1327414753 |
|
|
Jul 26 07:19:00 PM PDT 24 |
Jul 26 07:19:47 PM PDT 24 |
7059027200 ps |
| T1207 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3055747081 |
|
|
Jul 26 07:19:11 PM PDT 24 |
Jul 26 07:19:25 PM PDT 24 |
32967700 ps |
| T1208 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.649222174 |
|
|
Jul 26 07:20:28 PM PDT 24 |
Jul 26 07:20:43 PM PDT 24 |
44289200 ps |
| T1209 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3763991041 |
|
|
Jul 26 07:18:35 PM PDT 24 |
Jul 26 07:18:51 PM PDT 24 |
70928400 ps |
| T1210 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.741590549 |
|
|
Jul 26 07:19:00 PM PDT 24 |
Jul 26 07:19:16 PM PDT 24 |
40227500 ps |
| T1211 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3958788409 |
|
|
Jul 26 07:19:41 PM PDT 24 |
Jul 26 07:20:00 PM PDT 24 |
200942600 ps |
| T1212 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1578248850 |
|
|
Jul 26 07:19:58 PM PDT 24 |
Jul 26 07:20:14 PM PDT 24 |
35767200 ps |
| T1213 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2928595211 |
|
|
Jul 26 07:18:37 PM PDT 24 |
Jul 26 07:18:56 PM PDT 24 |
68625100 ps |
| T1214 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2285538605 |
|
|
Jul 26 07:18:44 PM PDT 24 |
Jul 26 07:19:15 PM PDT 24 |
250519500 ps |
| T1215 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.2839291711 |
|
|
Jul 26 07:20:38 PM PDT 24 |
Jul 26 07:20:52 PM PDT 24 |
37836800 ps |
| T368 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.768899386 |
|
|
Jul 26 07:19:56 PM PDT 24 |
Jul 26 07:27:47 PM PDT 24 |
350957900 ps |
| T1216 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3105695259 |
|
|
Jul 26 07:18:59 PM PDT 24 |
Jul 26 07:19:19 PM PDT 24 |
1503069900 ps |
| T1217 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1592658986 |
|
|
Jul 26 07:20:49 PM PDT 24 |
Jul 26 07:21:03 PM PDT 24 |
31012200 ps |
| T1218 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.974659863 |
|
|
Jul 26 07:19:49 PM PDT 24 |
Jul 26 07:20:02 PM PDT 24 |
16884500 ps |
| T1219 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.4132519919 |
|
|
Jul 26 07:20:48 PM PDT 24 |
Jul 26 07:21:02 PM PDT 24 |
29380700 ps |
| T1220 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2503318018 |
|
|
Jul 26 07:19:41 PM PDT 24 |
Jul 26 07:20:16 PM PDT 24 |
302345600 ps |
| T1221 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2076385503 |
|
|
Jul 26 07:19:18 PM PDT 24 |
Jul 26 07:19:35 PM PDT 24 |
37400700 ps |
| T1222 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.494828040 |
|
|
Jul 26 07:20:00 PM PDT 24 |
Jul 26 07:20:18 PM PDT 24 |
114312900 ps |
| T1223 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1280480790 |
|
|
Jul 26 07:20:15 PM PDT 24 |
Jul 26 07:20:31 PM PDT 24 |
29911000 ps |
| T1224 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2306607983 |
|
|
Jul 26 07:18:35 PM PDT 24 |
Jul 26 07:18:49 PM PDT 24 |
17174400 ps |
| T1225 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3636327770 |
|
|
Jul 26 07:20:03 PM PDT 24 |
Jul 26 07:20:18 PM PDT 24 |
12326600 ps |
| T1226 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3947154234 |
|
|
Jul 26 07:19:09 PM PDT 24 |
Jul 26 07:19:22 PM PDT 24 |
15216800 ps |
| T280 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.479869999 |
|
|
Jul 26 07:18:43 PM PDT 24 |
Jul 26 07:18:57 PM PDT 24 |
50113300 ps |
| T1227 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3514034889 |
|
|
Jul 26 07:19:17 PM PDT 24 |
Jul 26 07:19:34 PM PDT 24 |
183865700 ps |
| T1228 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3748247015 |
|
|
Jul 26 07:20:48 PM PDT 24 |
Jul 26 07:21:01 PM PDT 24 |
24197600 ps |
| T1229 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3229246012 |
|
|
Jul 26 07:20:11 PM PDT 24 |
Jul 26 07:20:29 PM PDT 24 |
62520300 ps |
| T1230 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.261593532 |
|
|
Jul 26 07:20:28 PM PDT 24 |
Jul 26 07:20:44 PM PDT 24 |
194276600 ps |
| T1231 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2447606831 |
|
|
Jul 26 07:19:55 PM PDT 24 |
Jul 26 07:20:09 PM PDT 24 |
12697900 ps |
| T371 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.1099371396 |
|
|
Jul 26 07:19:57 PM PDT 24 |
Jul 26 07:27:40 PM PDT 24 |
192645600 ps |
| T1232 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1328502502 |
|
|
Jul 26 07:20:47 PM PDT 24 |
Jul 26 07:21:00 PM PDT 24 |
57357800 ps |
| T1233 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1661924559 |
|
|
Jul 26 07:18:55 PM PDT 24 |
Jul 26 07:19:26 PM PDT 24 |
63221100 ps |
| T1234 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2952221243 |
|
|
Jul 26 07:20:37 PM PDT 24 |
Jul 26 07:20:50 PM PDT 24 |
146792400 ps |
| T1235 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1720058672 |
|
|
Jul 26 07:20:39 PM PDT 24 |
Jul 26 07:20:53 PM PDT 24 |
17228800 ps |
| T1236 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3297078186 |
|
|
Jul 26 07:20:18 PM PDT 24 |
Jul 26 07:20:34 PM PDT 24 |
20054700 ps |
| T1237 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2661634521 |
|
|
Jul 26 07:20:30 PM PDT 24 |
Jul 26 07:20:45 PM PDT 24 |
57565800 ps |
| T1238 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.519784303 |
|
|
Jul 26 07:18:25 PM PDT 24 |
Jul 26 07:18:44 PM PDT 24 |
102230800 ps |
| T1239 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.853100251 |
|
|
Jul 26 07:18:24 PM PDT 24 |
Jul 26 07:18:55 PM PDT 24 |
27956200 ps |
| T1240 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3637704794 |
|
|
Jul 26 07:19:24 PM PDT 24 |
Jul 26 07:19:38 PM PDT 24 |
11499800 ps |
| T367 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.4095599428 |
|
|
Jul 26 07:18:54 PM PDT 24 |
Jul 26 07:34:01 PM PDT 24 |
6293944300 ps |
| T1241 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1806641194 |
|
|
Jul 26 07:19:50 PM PDT 24 |
Jul 26 07:20:07 PM PDT 24 |
138092600 ps |
| T1242 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1615729755 |
|
|
Jul 26 07:19:51 PM PDT 24 |
Jul 26 07:20:08 PM PDT 24 |
339945200 ps |
| T1243 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3478444177 |
|
|
Jul 26 07:20:20 PM PDT 24 |
Jul 26 07:20:33 PM PDT 24 |
20342200 ps |
| T1244 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2048883232 |
|
|
Jul 26 07:19:43 PM PDT 24 |
Jul 26 07:20:02 PM PDT 24 |
206655000 ps |
| T1245 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2573559324 |
|
|
Jul 26 07:19:00 PM PDT 24 |
Jul 26 07:19:14 PM PDT 24 |
61221200 ps |
| T1246 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.440744209 |
|
|
Jul 26 07:20:49 PM PDT 24 |
Jul 26 07:21:03 PM PDT 24 |
51913900 ps |
| T1247 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3388974112 |
|
|
Jul 26 07:19:57 PM PDT 24 |
Jul 26 07:20:13 PM PDT 24 |
151063300 ps |
| T1248 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.4275585481 |
|
|
Jul 26 07:20:38 PM PDT 24 |
Jul 26 07:20:52 PM PDT 24 |
17088000 ps |
| T1249 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.928571277 |
|
|
Jul 26 07:19:32 PM PDT 24 |
Jul 26 07:19:53 PM PDT 24 |
77741300 ps |
| T1250 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.4110465811 |
|
|
Jul 26 07:19:24 PM PDT 24 |
Jul 26 07:19:40 PM PDT 24 |
440316300 ps |
| T1251 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1051168303 |
|
|
Jul 26 07:20:31 PM PDT 24 |
Jul 26 07:20:45 PM PDT 24 |
18468200 ps |
| T1252 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3985580266 |
|
|
Jul 26 07:18:24 PM PDT 24 |
Jul 26 07:18:40 PM PDT 24 |
14491000 ps |