Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	271342	1		T1	2		T2	2		T3	2
all_values[1]	271342	1		T1	2		T2	2		T3	2
all_values[2]	271342	1		T1	2		T2	2		T3	2
all_values[3]	271342	1		T1	2		T2	2		T3	2
all_values[4]	271342	1		T1	2		T2	2		T3	2
all_values[5]	271342	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	549148	1		T1	12		T2	12		T3	12
auto[1]	1078904	1		T20	14576		T24	43800		T32	3264

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	801731	1		T1	7		T2	7		T3	7
auto[1]	826321	1		T1	5		T2	5		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	271181	1		T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	161	1		T233	5		T234	4		T235	5
all_values[1]	auto[0]	auto[1]	271201	1		T1	2		T2	2		T3	2
all_values[1]	auto[1]	auto[1]	141	1		T233	4		T234	4		T235	1
all_values[2]	auto[0]	auto[0]	1645	1		T1	2		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	63	1		T234	2		T235	2		T314	2
all_values[2]	auto[1]	auto[0]	269580	1		T20	3644		T24	10950		T32	816
all_values[2]	auto[1]	auto[1]	54	1		T233	3		T234	4		T235	1
all_values[3]	auto[0]	auto[0]	1618	1		T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	59	1		T233	1		T234	2		T235	2
all_values[3]	auto[1]	auto[0]	82492	1		T20	1822		T24	1825		T32	232
all_values[3]	auto[1]	auto[1]	187173	1		T20	1822		T24	9125		T32	584
all_values[4]	auto[0]	auto[0]	1143	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	550	1		T1	1		T2	1		T3	1
all_values[4]	auto[1]	auto[0]	174054	1		T20	1822		T24	9125		T32	524
all_values[4]	auto[1]	auto[1]	95595	1		T20	1822		T24	1825		T32	292
all_values[5]	auto[0]	auto[0]	1594	1		T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	94	1		T5	1		T33	1		T34	1
all_values[5]	auto[1]	auto[0]	269605	1		T20	3644		T24	10950		T32	816
all_values[5]	auto[1]	auto[1]	49	1		T314	2		T313	1		T318	3