Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	237228	1		T1	340		T2	1575		T3	402
auto[FlashEraseBank]	260081	1		T2	1625		T4	1		T5	404

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	245659	1		T1	11		T2	823		T3	12
auto[FlashOpProgram]	231596	1		T1	320		T2	2377		T3	384
auto[FlashOpErase]	16054	1		T1	9		T3	6		T17	1
auto[FlashOpInvalid]	4000	1		T41	200		T98	200		T202	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	245659	1		T1	11		T2	823		T3	12
op[FlashOpProgram]	231596	1		T1	320		T2	2377		T3	384
op[FlashOpErase]	16054	1		T1	9		T3	6		T17	1
read_erase_read	567	1		T1	5		T3	1		T38	1
read_prog_read	844	1		T2	12		T38	5		T52	1

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	353908	1		T2	2782		T4	1		T17	4
auto[FlashPartInfo]	139477	1		T1	340		T2	386		T3	402
auto[FlashPartInfo1]	999	1		T2	4		T5	2		T38	3
auto[FlashPartInfo2]	2925	1		T2	28		T5	7		T37	1

---

Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	173863	1		T2	556		T17	2		T5	962
auto[FlashPartData]	auto[FlashOpProgram]	172462	1		T2	2226		T4	1		T17	1
auto[FlashPartData]	auto[FlashOpErase]	3667	1		T17	1		T41	99		T38	1
auto[FlashPartData]	auto[FlashOpInvalid]	3916	1		T41	198		T98	194		T202	192
auto[FlashPartInfo]	auto[FlashOpRead]	69046	1		T1	11		T2	248		T3	12
auto[FlashPartInfo]	auto[FlashOpProgram]	58008	1		T1	320		T2	138		T3	384
auto[FlashPartInfo]	auto[FlashOpErase]	12349	1		T1	9		T3	6		T41	1
auto[FlashPartInfo]	auto[FlashOpInvalid]	74	1		T41	2		T98	4		T202	8
auto[FlashPartInfo1]	auto[FlashOpRead]	825	1		T2	4		T5	2		T38	3
auto[FlashPartInfo1]	auto[FlashOpProgram]	165	1		T98	1		T111	32		T219	1
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T98	1		T386	1		T387	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	6	1		T98	2		T386	2		T387	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1925	1		T2	15		T5	7		T22	2
auto[FlashPartInfo2]	auto[FlashOpProgram]	961	1		T2	13		T37	1		T38	5
auto[FlashPartInfo2]	auto[FlashOpErase]	35	1		T59	1		T388	2		T130	2
auto[FlashPartInfo2]	auto[FlashOpInvalid]	4	1		T389	2		T390	2		-	-