Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31470	1		T17	4		T41	400		T28	24
auto[1]	47	1		T21	1		T71	1		T391	1
auto[2]	53	1		T118	1		T255	1		T195	1
auto[3]	203	1		T22	1		T23	1		T59	8

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7954	1		T17	1		T41	100		T28	6
evic_idx[1]	7938	1		T17	1		T41	100		T28	6
evic_idx[2]	7945	1		T17	1		T41	100		T28	6
evic_idx[3]	7936	1		T17	1		T41	100		T21	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30848	1		T17	4		T41	400		T98	400
evic_op[2]	332	1		T21	1		T22	1		T23	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7657	1		T17	1		T41	100		T98	100
evic_idx[0]	evic_op[1]	auto[1]	11	1		T199	2		T392	3		T393	5
evic_idx[0]	evic_op[1]	auto[2]	4	1		T394	1		T395	2		T396	1
evic_idx[0]	evic_op[1]	auto[3]	46	1		T59	1		T388	2		T397	3
evic_idx[0]	evic_op[2]	auto[0]	68	1		T56	4		T120	2		T398	7
evic_idx[0]	evic_op[2]	auto[1]	1	1		T399	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[2]	2	1		T198	1		T400	1		-	-
evic_idx[0]	evic_op[2]	auto[3]	15	1		T22	1		T23	1		T36	1
evic_idx[1]	evic_op[1]	auto[0]	7656	1		T17	1		T41	100		T98	100
evic_idx[1]	evic_op[1]	auto[1]	8	1		T199	2		T392	2		T393	4
evic_idx[1]	evic_op[1]	auto[2]	9	1		T394	3		T401	1		T395	2
evic_idx[1]	evic_op[1]	auto[3]	39	1		T59	1		T388	3		T397	5
evic_idx[1]	evic_op[2]	auto[0]	66	1		T56	4		T120	2		T398	7
evic_idx[1]	evic_op[2]	auto[1]	1	1		T71	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[2]	3	1		T255	1		T195	1		T198	1
evic_idx[1]	evic_op[2]	auto[3]	7	1		T402	1		T403	1		T404	1
evic_idx[2]	evic_op[1]	auto[0]	7658	1		T17	1		T41	100		T98	100
evic_idx[2]	evic_op[1]	auto[1]	10	1		T199	3		T392	3		T393	2
evic_idx[2]	evic_op[1]	auto[2]	7	1		T394	2		T395	2		T396	1
evic_idx[2]	evic_op[1]	auto[3]	37	1		T59	4		T388	3		T397	2
evic_idx[2]	evic_op[2]	auto[0]	67	1		T56	4		T185	1		T120	2
evic_idx[2]	evic_op[2]	auto[1]	5	1		T391	1		T72	1		T73	1
evic_idx[2]	evic_op[2]	auto[2]	4	1		T118	1		T198	2		T399	1
evic_idx[2]	evic_op[2]	auto[3]	10	1		T405	1		T182	1		T183	1
evic_idx[3]	evic_op[1]	auto[0]	7656	1		T17	1		T41	100		T98	100
evic_idx[3]	evic_op[1]	auto[1]	8	1		T199	1		T392	1		T393	3
evic_idx[3]	evic_op[1]	auto[2]	4	1		T394	2		T396	1		T406	1
evic_idx[3]	evic_op[1]	auto[3]	38	1		T59	2		T388	3		T397	2
evic_idx[3]	evic_op[2]	auto[0]	65	1		T56	4		T185	1		T120	2
evic_idx[3]	evic_op[2]	auto[1]	3	1		T21	1		T407	1		T73	1
evic_idx[3]	evic_op[2]	auto[2]	4	1		T198	1		T408	1		T409	1
evic_idx[3]	evic_op[2]	auto[3]	11	1		T186	1		T410	1		T197	1