Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	6299	1		T319	1616		T320	2156		T321	2527
rd_lvl[2]	36095	1		T192	2443		T319	913		T322	7480
rd_lvl[3]	21043	1		T24	4734		T192	1967		T205	845
rd_lvl[4]	25411	1		T24	4391		T192	929		T205	747
rd_lvl[5]	16302	1		T192	1581		T205	95		T319	76
rd_lvl[6]	21874	1		T192	2201		T205	163		T319	19
rd_lvl[7]	9400	1		T32	379		T192	290		T319	8
rd_lvl[8]	6602	1		T32	84		T192	290		T323	5
rd_lvl[9]	5136	1		T32	62		T216	606		T192	290
rd_lvl[10]	6677	1		T32	59		T216	1092		T205	1
rd_lvl[11]	2097	1		T30	267		T31	338		T324	471
rd_lvl[12]	8553	1		T20	1541		T30	113		T258	1290
rd_lvl[13]	3698	1		T20	281		T29	304		T205	164
rd_lvl[14]	5197	1		T29	131		T30	168		T31	47
rd_lvl[15]	1067	1		T325	247		T326	285		T327	89