Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	271342	1		T1	2		T2	2		T3	2
all_pins[1]	271342	1		T1	2		T2	2		T3	2
all_pins[2]	271342	1		T1	2		T2	2		T3	2
all_pins[3]	271342	1		T1	2		T2	2		T3	2
all_pins[4]	271342	1		T1	2		T2	2		T3	2
all_pins[5]	271342	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1343590	1		T1	12		T2	12		T3	12
values[0x1]	284462	1		T20	3644		T24	12109		T32	877
transitions[0x0=>0x1]	261260	1		T20	3644		T24	10950		T32	816
transitions[0x1=>0x0]	261243	1		T20	3644		T24	10950		T32	816

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	271181	1		T1	2		T2	2		T3	2
all_pins[0]	values[0x1]	161	1		T233	5		T234	4		T235	5
all_pins[0]	transitions[0x0=>0x1]	102	1		T233	2		T234	4		T235	5
all_pins[0]	transitions[0x1=>0x0]	82	1		T233	1		T234	4		T235	1
all_pins[1]	values[0x0]	271201	1		T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	141	1		T233	4		T234	4		T235	1
all_pins[1]	transitions[0x0=>0x1]	121	1		T233	4		T234	2		T235	1
all_pins[1]	transitions[0x1=>0x0]	2192	1		T325	661		T333	190		T334	1307
all_pins[2]	values[0x0]	269130	1		T1	2		T2	2		T3	2
all_pins[2]	values[0x1]	2212	1		T325	661		T333	190		T334	1307
all_pins[2]	transitions[0x0=>0x1]	48	1		T233	2		T234	3		T235	1
all_pins[2]	transitions[0x1=>0x0]	176094	1		T20	1822		T24	9125		T32	584
all_pins[3]	values[0x0]	93084	1		T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	178258	1		T20	1822		T24	9125		T32	584
all_pins[3]	transitions[0x0=>0x1]	157339	1		T20	1822		T24	7966		T32	523
all_pins[3]	transitions[0x1=>0x0]	82722	1		T20	1822		T24	1825		T32	232
all_pins[4]	values[0x0]	167701	1		T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	103641	1		T20	1822		T24	2984		T32	293
all_pins[4]	transitions[0x0=>0x1]	103629	1		T20	1822		T24	2984		T32	293
all_pins[4]	transitions[0x1=>0x0]	37	1		T314	2		T318	1		T316	2
all_pins[5]	values[0x0]	271293	1		T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	49	1		T314	2		T313	1		T318	3
all_pins[5]	transitions[0x0=>0x1]	21	1		T314	1		T318	1		T316	2
all_pins[5]	transitions[0x1=>0x0]	116	1		T233	4		T234	3		T235	4