Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1		T233	7		T234	7		T235	7
all_values[1]	281	1		T233	7		T234	7		T235	7
all_values[2]	281	1		T233	7		T234	7		T235	7
all_values[3]	281	1		T233	7		T234	7		T235	7
all_values[4]	281	1		T233	7		T234	7		T235	7
all_values[5]	281	1		T233	7		T234	7		T235	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	984	1		T233	19		T234	25		T235	24
auto[1]	702	1		T233	23		T234	17		T235	18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	541	1		T233	13		T234	14		T235	11
auto[1]	1145	1		T233	29		T234	28		T235	31

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	993	1		T233	28		T234	22		T235	23
auto[1]	693	1		T233	14		T234	20		T235	19

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	97	1		T233	2		T234	3		T235	2
all_values[0]	auto[0]	auto[1]	auto[1]	73	1		T233	3		T234	1		T235	3
all_values[0]	auto[1]	auto[0]	auto[1]	68	1		T233	1		T234	2		T235	2
all_values[0]	auto[1]	auto[1]	auto[1]	43	1		T233	1		T234	1		T312	3
all_values[1]	auto[0]	auto[0]	auto[1]	113	1		T233	3		T234	3		T235	4
all_values[1]	auto[0]	auto[1]	auto[1]	61	1		T233	3		T312	2		T313	1
all_values[1]	auto[1]	auto[0]	auto[1]	60	1		T233	1		T235	1		T314	3
all_values[1]	auto[1]	auto[1]	auto[1]	47	1		T234	4		T235	2		T312	2
all_values[2]	auto[0]	auto[0]	auto[0]	104	1		T233	2		T235	2		T314	2
all_values[2]	auto[0]	auto[1]	auto[0]	60	1		T233	2		T234	1		T235	2
all_values[2]	auto[1]	auto[0]	auto[1]	74	1		T233	1		T234	4		T235	2
all_values[2]	auto[1]	auto[1]	auto[1]	43	1		T233	2		T234	2		T235	1
all_values[3]	auto[0]	auto[0]	auto[0]	86	1		T233	2		T234	3		T235	1
all_values[3]	auto[0]	auto[1]	auto[0]	79	1		T233	2		T314	3		T312	3
all_values[3]	auto[1]	auto[0]	auto[1]	60	1		T233	1		T235	2		T312	2
all_values[3]	auto[1]	auto[1]	auto[1]	56	1		T233	2		T234	4		T235	4
all_values[4]	auto[0]	auto[0]	auto[0]	58	1		T233	1		T234	3		T312	2
all_values[4]	auto[0]	auto[0]	auto[1]	33	1		T235	2		T314	1		T313	1
all_values[4]	auto[0]	auto[1]	auto[0]	42	1		T233	2		T315	2		T316	1
all_values[4]	auto[0]	auto[1]	auto[1]	30	1		T233	2		T234	1		T235	1
all_values[4]	auto[1]	auto[0]	auto[1]	72	1		T234	2		T235	2		T314	3
all_values[4]	auto[1]	auto[1]	auto[1]	46	1		T233	2		T234	1		T235	2
all_values[5]	auto[0]	auto[0]	auto[0]	62	1		T234	5		T235	4		T313	1
all_values[5]	auto[0]	auto[0]	auto[1]	27	1		T233	2		T313	1		T317	1
all_values[5]	auto[0]	auto[1]	auto[0]	50	1		T233	2		T234	2		T235	2
all_values[5]	auto[0]	auto[1]	auto[1]	18	1		T314	1		T318	2		T315	1
all_values[5]	auto[1]	auto[0]	auto[1]	70	1		T233	3		T314	2		T312	4
all_values[5]	auto[1]	auto[1]	auto[1]	54	1		T235	1		T314	1		T312	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal