| T1085 |
/workspace/coverage/default/36.flash_ctrl_hw_sec_otp.2860617758 |
|
|
Jul 27 07:30:49 PM PDT 24 |
Jul 27 07:32:20 PM PDT 24 |
10115493500 ps |
| T1086 |
/workspace/coverage/default/55.flash_ctrl_connect.3295579721 |
|
|
Jul 27 07:32:10 PM PDT 24 |
Jul 27 07:32:25 PM PDT 24 |
16442900 ps |
| T1087 |
/workspace/coverage/default/0.flash_ctrl_full_mem_access.1375486667 |
|
|
Jul 27 07:12:58 PM PDT 24 |
Jul 27 08:01:54 PM PDT 24 |
378458611900 ps |
| T1088 |
/workspace/coverage/default/5.flash_ctrl_rw.2002934141 |
|
|
Jul 27 07:20:51 PM PDT 24 |
Jul 27 07:28:42 PM PDT 24 |
3662161500 ps |
| T357 |
/workspace/coverage/default/5.flash_ctrl_disable.3704242187 |
|
|
Jul 27 07:21:10 PM PDT 24 |
Jul 27 07:21:32 PM PDT 24 |
11161200 ps |
| T1089 |
/workspace/coverage/default/5.flash_ctrl_rand_ops.2221516555 |
|
|
Jul 27 07:20:35 PM PDT 24 |
Jul 27 07:37:57 PM PDT 24 |
130658400 ps |
| T1090 |
/workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.4014811625 |
|
|
Jul 27 07:18:48 PM PDT 24 |
Jul 27 07:24:22 PM PDT 24 |
10012917300 ps |
| T1091 |
/workspace/coverage/default/5.flash_ctrl_mp_regions.2290881298 |
|
|
Jul 27 07:20:42 PM PDT 24 |
Jul 27 07:33:25 PM PDT 24 |
19704802400 ps |
| T1092 |
/workspace/coverage/default/13.flash_ctrl_rw.2123428132 |
|
|
Jul 27 07:25:52 PM PDT 24 |
Jul 27 07:36:52 PM PDT 24 |
3620203600 ps |
| T1093 |
/workspace/coverage/default/28.flash_ctrl_smoke.1351981752 |
|
|
Jul 27 07:29:51 PM PDT 24 |
Jul 27 07:33:04 PM PDT 24 |
42658600 ps |
| T1094 |
/workspace/coverage/default/45.flash_ctrl_sec_info_access.1443222600 |
|
|
Jul 27 07:31:47 PM PDT 24 |
Jul 27 07:33:06 PM PDT 24 |
2137726600 ps |
| T1095 |
/workspace/coverage/default/6.flash_ctrl_mp_regions.382751805 |
|
|
Jul 27 07:21:30 PM PDT 24 |
Jul 27 07:24:28 PM PDT 24 |
8054144900 ps |
| T1096 |
/workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.3439076673 |
|
|
Jul 27 07:22:28 PM PDT 24 |
Jul 27 07:26:10 PM PDT 24 |
99988123000 ps |
| T1097 |
/workspace/coverage/default/27.flash_ctrl_connect.2314825315 |
|
|
Jul 27 07:29:51 PM PDT 24 |
Jul 27 07:30:04 PM PDT 24 |
38341100 ps |
| T1098 |
/workspace/coverage/default/12.flash_ctrl_sec_info_access.3224510960 |
|
|
Jul 27 07:25:37 PM PDT 24 |
Jul 27 07:26:49 PM PDT 24 |
7051626900 ps |
| T1099 |
/workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.347441356 |
|
|
Jul 27 07:13:12 PM PDT 24 |
Jul 27 07:13:34 PM PDT 24 |
47533600 ps |
| T334 |
/workspace/coverage/default/37.flash_ctrl_intr_rd.52059880 |
|
|
Jul 27 07:30:57 PM PDT 24 |
Jul 27 07:34:15 PM PDT 24 |
2471336400 ps |
| T1100 |
/workspace/coverage/default/48.flash_ctrl_alert_test.2391058619 |
|
|
Jul 27 07:31:58 PM PDT 24 |
Jul 27 07:32:12 PM PDT 24 |
40501100 ps |
| T1101 |
/workspace/coverage/default/9.flash_ctrl_mp_regions.4275428263 |
|
|
Jul 27 07:23:45 PM PDT 24 |
Jul 27 07:26:05 PM PDT 24 |
5149297400 ps |
| T1102 |
/workspace/coverage/default/8.flash_ctrl_connect.164852159 |
|
|
Jul 27 07:23:35 PM PDT 24 |
Jul 27 07:23:48 PM PDT 24 |
22029700 ps |
| T1103 |
/workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.1374623615 |
|
|
Jul 27 07:26:27 PM PDT 24 |
Jul 27 07:26:40 PM PDT 24 |
26222700 ps |
| T1104 |
/workspace/coverage/default/13.flash_ctrl_wo.1820346623 |
|
|
Jul 27 07:25:45 PM PDT 24 |
Jul 27 07:28:19 PM PDT 24 |
2159874600 ps |
| T1105 |
/workspace/coverage/default/12.flash_ctrl_lcmgr_intg.172600784 |
|
|
Jul 27 07:25:36 PM PDT 24 |
Jul 27 07:25:49 PM PDT 24 |
16172200 ps |
| T1106 |
/workspace/coverage/default/5.flash_ctrl_hw_rma_reset.3032000384 |
|
|
Jul 27 07:20:34 PM PDT 24 |
Jul 27 07:36:13 PM PDT 24 |
160187802500 ps |
| T366 |
/workspace/coverage/default/26.flash_ctrl_sec_info_access.2200684142 |
|
|
Jul 27 07:29:34 PM PDT 24 |
Jul 27 07:31:01 PM PDT 24 |
1031934300 ps |
| T1107 |
/workspace/coverage/default/16.flash_ctrl_mp_regions.1532108320 |
|
|
Jul 27 07:26:58 PM PDT 24 |
Jul 27 07:32:08 PM PDT 24 |
19441667600 ps |
| T1108 |
/workspace/coverage/default/20.flash_ctrl_intr_rd.1860195634 |
|
|
Jul 27 07:28:23 PM PDT 24 |
Jul 27 07:30:59 PM PDT 24 |
1532706700 ps |
| T1109 |
/workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.3792698401 |
|
|
Jul 27 07:24:02 PM PDT 24 |
Jul 27 07:27:31 PM PDT 24 |
50679481700 ps |
| T1110 |
/workspace/coverage/default/0.flash_ctrl_otp_reset.4224384389 |
|
|
Jul 27 07:12:59 PM PDT 24 |
Jul 27 07:15:08 PM PDT 24 |
151512400 ps |
| T1111 |
/workspace/coverage/default/12.flash_ctrl_prog_reset.3921046007 |
|
|
Jul 27 07:25:29 PM PDT 24 |
Jul 27 07:25:42 PM PDT 24 |
84581000 ps |
| T1112 |
/workspace/coverage/default/41.flash_ctrl_otp_reset.1426189612 |
|
|
Jul 27 07:31:25 PM PDT 24 |
Jul 27 07:33:35 PM PDT 24 |
71219700 ps |
| T187 |
/workspace/coverage/default/9.flash_ctrl_ro_derr.1016501049 |
|
|
Jul 27 07:23:54 PM PDT 24 |
Jul 27 07:25:48 PM PDT 24 |
479802300 ps |
| T1113 |
/workspace/coverage/default/4.flash_ctrl_phy_arb.1597678949 |
|
|
Jul 27 07:19:07 PM PDT 24 |
Jul 27 07:24:28 PM PDT 24 |
78641300 ps |
| T1114 |
/workspace/coverage/default/14.flash_ctrl_wo.2982402983 |
|
|
Jul 27 07:26:11 PM PDT 24 |
Jul 27 07:28:50 PM PDT 24 |
3302434700 ps |
| T1115 |
/workspace/coverage/default/2.flash_ctrl_smoke_hw.4255171717 |
|
|
Jul 27 07:16:22 PM PDT 24 |
Jul 27 07:16:45 PM PDT 24 |
23171500 ps |
| T1116 |
/workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.1272655225 |
|
|
Jul 27 07:30:07 PM PDT 24 |
Jul 27 07:30:36 PM PDT 24 |
52642600 ps |
| T1117 |
/workspace/coverage/default/19.flash_ctrl_rand_ops.3918901586 |
|
|
Jul 27 07:28:10 PM PDT 24 |
Jul 27 07:42:59 PM PDT 24 |
873795600 ps |
| T1118 |
/workspace/coverage/default/33.flash_ctrl_otp_reset.4285128351 |
|
|
Jul 27 07:30:32 PM PDT 24 |
Jul 27 07:32:45 PM PDT 24 |
39362900 ps |
| T377 |
/workspace/coverage/default/32.flash_ctrl_sec_info_access.396758498 |
|
|
Jul 27 07:30:24 PM PDT 24 |
Jul 27 07:31:20 PM PDT 24 |
660227200 ps |
| T1119 |
/workspace/coverage/default/3.flash_ctrl_fs_sup.3799952010 |
|
|
Jul 27 07:18:39 PM PDT 24 |
Jul 27 07:19:17 PM PDT 24 |
610651800 ps |
| T1120 |
/workspace/coverage/default/7.flash_ctrl_mp_regions.1446581625 |
|
|
Jul 27 07:22:18 PM PDT 24 |
Jul 27 07:29:57 PM PDT 24 |
24424733700 ps |
| T1121 |
/workspace/coverage/default/5.flash_ctrl_wo.1910352465 |
|
|
Jul 27 07:20:51 PM PDT 24 |
Jul 27 07:24:03 PM PDT 24 |
5657514400 ps |
| T1122 |
/workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.560063541 |
|
|
Jul 27 07:25:29 PM PDT 24 |
Jul 27 07:25:59 PM PDT 24 |
66034500 ps |
| T1123 |
/workspace/coverage/default/0.flash_ctrl_serr_counter.2503702485 |
|
|
Jul 27 07:13:18 PM PDT 24 |
Jul 27 07:14:48 PM PDT 24 |
5692200900 ps |
| T1124 |
/workspace/coverage/default/41.flash_ctrl_hw_sec_otp.3782029062 |
|
|
Jul 27 07:31:22 PM PDT 24 |
Jul 27 07:33:43 PM PDT 24 |
7586102400 ps |
| T1125 |
/workspace/coverage/default/39.flash_ctrl_smoke.432152602 |
|
|
Jul 27 07:31:13 PM PDT 24 |
Jul 27 07:32:51 PM PDT 24 |
66162400 ps |
| T1126 |
/workspace/coverage/default/19.flash_ctrl_phy_arb.3994407264 |
|
|
Jul 27 07:28:08 PM PDT 24 |
Jul 27 07:31:39 PM PDT 24 |
1853813800 ps |
| T1127 |
/workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.2050110328 |
|
|
Jul 27 07:27:35 PM PDT 24 |
Jul 27 07:30:04 PM PDT 24 |
10012006600 ps |
| T1128 |
/workspace/coverage/default/20.flash_ctrl_connect.3813652898 |
|
|
Jul 27 07:28:34 PM PDT 24 |
Jul 27 07:28:49 PM PDT 24 |
25485800 ps |
| T1129 |
/workspace/coverage/default/15.flash_ctrl_ro.4073202969 |
|
|
Jul 27 07:26:39 PM PDT 24 |
Jul 27 07:28:41 PM PDT 24 |
2399103900 ps |
| T1130 |
/workspace/coverage/default/4.flash_ctrl_alert_test.1049074456 |
|
|
Jul 27 07:20:33 PM PDT 24 |
Jul 27 07:20:47 PM PDT 24 |
20687200 ps |
| T1131 |
/workspace/coverage/default/5.flash_ctrl_otp_reset.2945621103 |
|
|
Jul 27 07:20:37 PM PDT 24 |
Jul 27 07:22:48 PM PDT 24 |
37266500 ps |
| T1132 |
/workspace/coverage/default/9.flash_ctrl_intr_wr.277873490 |
|
|
Jul 27 07:24:02 PM PDT 24 |
Jul 27 07:25:02 PM PDT 24 |
11241447400 ps |
| T190 |
/workspace/coverage/default/3.flash_ctrl_integrity.847762075 |
|
|
Jul 27 07:18:31 PM PDT 24 |
Jul 27 07:27:17 PM PDT 24 |
13406798200 ps |
| T1133 |
/workspace/coverage/default/37.flash_ctrl_smoke.2576601300 |
|
|
Jul 27 07:30:57 PM PDT 24 |
Jul 27 07:32:11 PM PDT 24 |
118780700 ps |
| T1134 |
/workspace/coverage/default/4.flash_ctrl_hw_rma_reset.1729601377 |
|
|
Jul 27 07:19:16 PM PDT 24 |
Jul 27 07:34:12 PM PDT 24 |
110155660000 ps |
| T1135 |
/workspace/coverage/default/59.flash_ctrl_otp_reset.1855562503 |
|
|
Jul 27 07:32:09 PM PDT 24 |
Jul 27 07:34:19 PM PDT 24 |
38554100 ps |
| T1136 |
/workspace/coverage/default/34.flash_ctrl_disable.3823762413 |
|
|
Jul 27 07:30:40 PM PDT 24 |
Jul 27 07:31:02 PM PDT 24 |
19134700 ps |
| T233 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.910804052 |
|
|
Jul 27 06:55:31 PM PDT 24 |
Jul 27 06:55:44 PM PDT 24 |
24858900 ps |
| T234 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2933178910 |
|
|
Jul 27 06:55:46 PM PDT 24 |
Jul 27 06:56:00 PM PDT 24 |
84371400 ps |
| T261 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3804307964 |
|
|
Jul 27 06:54:22 PM PDT 24 |
Jul 27 06:54:35 PM PDT 24 |
28755600 ps |
| T1137 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3261356602 |
|
|
Jul 27 06:54:49 PM PDT 24 |
Jul 27 06:55:05 PM PDT 24 |
14420400 ps |
| T235 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3777574173 |
|
|
Jul 27 06:55:39 PM PDT 24 |
Jul 27 06:55:53 PM PDT 24 |
15364900 ps |
| T314 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2923394561 |
|
|
Jul 27 06:56:13 PM PDT 24 |
Jul 27 06:56:26 PM PDT 24 |
72487100 ps |
| T312 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1195701982 |
|
|
Jul 27 06:55:54 PM PDT 24 |
Jul 27 06:56:07 PM PDT 24 |
28027300 ps |
| T60 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.75330140 |
|
|
Jul 27 06:54:56 PM PDT 24 |
Jul 27 07:10:02 PM PDT 24 |
1605686100 ps |
| T61 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.138893625 |
|
|
Jul 27 06:55:30 PM PDT 24 |
Jul 27 06:55:47 PM PDT 24 |
121702200 ps |
| T92 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2540788802 |
|
|
Jul 27 06:55:57 PM PDT 24 |
Jul 27 06:56:14 PM PDT 24 |
206997500 ps |
| T1138 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1380095715 |
|
|
Jul 27 06:55:54 PM PDT 24 |
Jul 27 06:56:10 PM PDT 24 |
35457800 ps |
| T62 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.628238176 |
|
|
Jul 27 06:54:14 PM PDT 24 |
Jul 27 06:54:33 PM PDT 24 |
162885400 ps |
| T1139 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3982153063 |
|
|
Jul 27 06:55:29 PM PDT 24 |
Jul 27 06:55:45 PM PDT 24 |
41287500 ps |
| T93 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3733088885 |
|
|
Jul 27 06:55:55 PM PDT 24 |
Jul 27 07:02:26 PM PDT 24 |
684428900 ps |
| T229 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3796558316 |
|
|
Jul 27 06:55:01 PM PDT 24 |
Jul 27 06:55:15 PM PDT 24 |
19068600 ps |
| T227 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.867562787 |
|
|
Jul 27 06:55:21 PM PDT 24 |
Jul 27 06:55:39 PM PDT 24 |
306080500 ps |
| T313 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2464326536 |
|
|
Jul 27 06:55:55 PM PDT 24 |
Jul 27 06:56:09 PM PDT 24 |
27733600 ps |
| T1140 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2868664287 |
|
|
Jul 27 06:54:06 PM PDT 24 |
Jul 27 06:54:22 PM PDT 24 |
20991600 ps |
| T1141 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2164806953 |
|
|
Jul 27 06:55:30 PM PDT 24 |
Jul 27 06:55:45 PM PDT 24 |
19653800 ps |
| T206 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.372004879 |
|
|
Jul 27 06:55:46 PM PDT 24 |
Jul 27 06:56:05 PM PDT 24 |
77556500 ps |
| T228 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3954789947 |
|
|
Jul 27 06:54:31 PM PDT 24 |
Jul 27 06:56:22 PM PDT 24 |
22099045400 ps |
| T207 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2961728370 |
|
|
Jul 27 06:55:06 PM PDT 24 |
Jul 27 06:55:27 PM PDT 24 |
85266900 ps |
| T208 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2942865224 |
|
|
Jul 27 06:55:22 PM PDT 24 |
Jul 27 06:55:38 PM PDT 24 |
114283900 ps |
| T318 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.910671700 |
|
|
Jul 27 06:56:13 PM PDT 24 |
Jul 27 06:56:26 PM PDT 24 |
52451700 ps |
| T317 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3063358503 |
|
|
Jul 27 06:54:07 PM PDT 24 |
Jul 27 06:54:21 PM PDT 24 |
16542100 ps |
| T1142 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.3310291120 |
|
|
Jul 27 06:55:53 PM PDT 24 |
Jul 27 06:56:09 PM PDT 24 |
12236800 ps |
| T262 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1103369668 |
|
|
Jul 27 06:54:01 PM PDT 24 |
Jul 27 06:54:14 PM PDT 24 |
21312000 ps |
| T238 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1277633396 |
|
|
Jul 27 06:54:35 PM PDT 24 |
Jul 27 06:54:54 PM PDT 24 |
564613000 ps |
| T265 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1970520595 |
|
|
Jul 27 06:54:52 PM PDT 24 |
Jul 27 06:55:08 PM PDT 24 |
112257200 ps |
| T225 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3959458589 |
|
|
Jul 27 06:55:50 PM PDT 24 |
Jul 27 07:03:27 PM PDT 24 |
428150600 ps |
| T239 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.266285743 |
|
|
Jul 27 06:55:47 PM PDT 24 |
Jul 27 06:56:07 PM PDT 24 |
155027800 ps |
| T266 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2633023880 |
|
|
Jul 27 06:54:01 PM PDT 24 |
Jul 27 06:54:18 PM PDT 24 |
118082300 ps |
| T267 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2914193814 |
|
|
Jul 27 06:55:20 PM PDT 24 |
Jul 27 06:55:40 PM PDT 24 |
1550924300 ps |
| T1143 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1709439967 |
|
|
Jul 27 06:55:13 PM PDT 24 |
Jul 27 06:55:26 PM PDT 24 |
113596000 ps |
| T315 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2318790769 |
|
|
Jul 27 06:56:13 PM PDT 24 |
Jul 27 06:56:27 PM PDT 24 |
30108100 ps |
| T1144 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.319709649 |
|
|
Jul 27 06:55:47 PM PDT 24 |
Jul 27 06:56:00 PM PDT 24 |
13736400 ps |
| T230 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.711974719 |
|
|
Jul 27 06:53:54 PM PDT 24 |
Jul 27 06:54:13 PM PDT 24 |
113466700 ps |
| T259 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2783021924 |
|
|
Jul 27 06:55:13 PM PDT 24 |
Jul 27 06:55:28 PM PDT 24 |
45521900 ps |
| T1145 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.608626120 |
|
|
Jul 27 06:54:34 PM PDT 24 |
Jul 27 06:54:50 PM PDT 24 |
22882100 ps |
| T316 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2563122534 |
|
|
Jul 27 06:55:12 PM PDT 24 |
Jul 27 06:55:26 PM PDT 24 |
53120200 ps |
| T268 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1858928875 |
|
|
Jul 27 06:55:56 PM PDT 24 |
Jul 27 06:56:13 PM PDT 24 |
20545600 ps |
| T269 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.164338999 |
|
|
Jul 27 06:54:48 PM PDT 24 |
Jul 27 06:55:03 PM PDT 24 |
97576600 ps |
| T1146 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.4001764719 |
|
|
Jul 27 06:55:02 PM PDT 24 |
Jul 27 06:55:18 PM PDT 24 |
11783900 ps |
| T1147 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2076220174 |
|
|
Jul 27 06:55:47 PM PDT 24 |
Jul 27 06:56:00 PM PDT 24 |
23647500 ps |
| T236 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.4220392604 |
|
|
Jul 27 06:55:14 PM PDT 24 |
Jul 27 06:55:33 PM PDT 24 |
99518700 ps |
| T1148 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.1733141945 |
|
|
Jul 27 06:55:56 PM PDT 24 |
Jul 27 06:56:10 PM PDT 24 |
43066800 ps |
| T1149 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.216647454 |
|
|
Jul 27 06:55:22 PM PDT 24 |
Jul 27 06:55:42 PM PDT 24 |
445348400 ps |
| T231 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.434508014 |
|
|
Jul 27 06:55:02 PM PDT 24 |
Jul 27 06:55:23 PM PDT 24 |
131075200 ps |
| T1150 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1259393406 |
|
|
Jul 27 06:55:48 PM PDT 24 |
Jul 27 06:56:04 PM PDT 24 |
70622600 ps |
| T1151 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2746294644 |
|
|
Jul 27 06:55:29 PM PDT 24 |
Jul 27 06:55:43 PM PDT 24 |
14511800 ps |
| T1152 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1133335697 |
|
|
Jul 27 06:54:54 PM PDT 24 |
Jul 27 06:55:08 PM PDT 24 |
28984800 ps |
| T1153 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2429534380 |
|
|
Jul 27 06:54:01 PM PDT 24 |
Jul 27 06:54:56 PM PDT 24 |
648966000 ps |
| T1154 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.4103057103 |
|
|
Jul 27 06:55:46 PM PDT 24 |
Jul 27 06:56:03 PM PDT 24 |
34132000 ps |
| T1155 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.1866986167 |
|
|
Jul 27 06:56:12 PM PDT 24 |
Jul 27 06:56:25 PM PDT 24 |
44475600 ps |
| T237 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1427797763 |
|
|
Jul 27 06:55:45 PM PDT 24 |
Jul 27 06:56:05 PM PDT 24 |
107765900 ps |
| T243 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3126657950 |
|
|
Jul 27 06:55:14 PM PDT 24 |
Jul 27 07:02:52 PM PDT 24 |
2375426300 ps |
| T1156 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3486865845 |
|
|
Jul 27 06:55:56 PM PDT 24 |
Jul 27 06:56:10 PM PDT 24 |
48299800 ps |
| T232 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1868778372 |
|
|
Jul 27 06:55:28 PM PDT 24 |
Jul 27 06:55:44 PM PDT 24 |
105497700 ps |
| T1157 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2694038274 |
|
|
Jul 27 06:55:03 PM PDT 24 |
Jul 27 06:55:19 PM PDT 24 |
157262700 ps |
| T1158 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.167848093 |
|
|
Jul 27 06:54:50 PM PDT 24 |
Jul 27 06:55:06 PM PDT 24 |
44527700 ps |
| T1159 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3838863909 |
|
|
Jul 27 06:54:06 PM PDT 24 |
Jul 27 06:54:20 PM PDT 24 |
93730800 ps |
| T1160 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3371290500 |
|
|
Jul 27 06:54:33 PM PDT 24 |
Jul 27 06:54:46 PM PDT 24 |
14464000 ps |
| T1161 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3460792813 |
|
|
Jul 27 06:55:06 PM PDT 24 |
Jul 27 06:55:26 PM PDT 24 |
233219600 ps |
| T335 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.41110435 |
|
|
Jul 27 06:54:15 PM PDT 24 |
Jul 27 06:54:35 PM PDT 24 |
444930200 ps |
| T276 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3478712969 |
|
|
Jul 27 06:54:01 PM PDT 24 |
Jul 27 06:54:41 PM PDT 24 |
7081533500 ps |
| T280 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.826134679 |
|
|
Jul 27 06:54:07 PM PDT 24 |
Jul 27 06:54:24 PM PDT 24 |
45479100 ps |
| T277 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.187102750 |
|
|
Jul 27 06:55:53 PM PDT 24 |
Jul 27 06:56:11 PM PDT 24 |
238005000 ps |
| T278 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3469184899 |
|
|
Jul 27 06:54:55 PM PDT 24 |
Jul 27 06:55:12 PM PDT 24 |
234290300 ps |
| T1162 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2049086818 |
|
|
Jul 27 06:55:29 PM PDT 24 |
Jul 27 06:55:44 PM PDT 24 |
40168000 ps |
| T1163 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3159712240 |
|
|
Jul 27 06:55:29 PM PDT 24 |
Jul 27 06:55:45 PM PDT 24 |
21472900 ps |
| T279 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3679244620 |
|
|
Jul 27 06:54:07 PM PDT 24 |
Jul 27 06:54:48 PM PDT 24 |
872349400 ps |
| T1164 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.512207626 |
|
|
Jul 27 06:55:06 PM PDT 24 |
Jul 27 06:55:25 PM PDT 24 |
167861000 ps |
| T1165 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2366234950 |
|
|
Jul 27 06:54:09 PM PDT 24 |
Jul 27 06:54:54 PM PDT 24 |
25027200 ps |
| T1166 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2888995793 |
|
|
Jul 27 06:56:11 PM PDT 24 |
Jul 27 06:56:24 PM PDT 24 |
26067700 ps |
| T281 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.523689003 |
|
|
Jul 27 06:54:01 PM PDT 24 |
Jul 27 06:54:19 PM PDT 24 |
103254400 ps |
| T1167 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2995973923 |
|
|
Jul 27 06:54:41 PM PDT 24 |
Jul 27 06:54:55 PM PDT 24 |
94802300 ps |
| T1168 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.373842634 |
|
|
Jul 27 06:55:20 PM PDT 24 |
Jul 27 06:55:40 PM PDT 24 |
62273400 ps |
| T1169 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.4138842002 |
|
|
Jul 27 06:56:00 PM PDT 24 |
Jul 27 06:56:14 PM PDT 24 |
14773900 ps |
| T282 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1950581871 |
|
|
Jul 27 06:54:41 PM PDT 24 |
Jul 27 06:55:19 PM PDT 24 |
3133911700 ps |
| T283 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.4102433838 |
|
|
Jul 27 06:54:40 PM PDT 24 |
Jul 27 06:55:33 PM PDT 24 |
5873799000 ps |
| T284 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3885451374 |
|
|
Jul 27 06:54:32 PM PDT 24 |
Jul 27 06:55:42 PM PDT 24 |
7114935400 ps |
| T1170 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3273508506 |
|
|
Jul 27 06:55:29 PM PDT 24 |
Jul 27 06:55:43 PM PDT 24 |
18461800 ps |
| T1171 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2185866425 |
|
|
Jul 27 06:56:12 PM PDT 24 |
Jul 27 06:56:26 PM PDT 24 |
15748100 ps |
| T1172 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1831605051 |
|
|
Jul 27 06:55:04 PM PDT 24 |
Jul 27 06:55:19 PM PDT 24 |
57835100 ps |
| T1173 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1269580145 |
|
|
Jul 27 06:56:14 PM PDT 24 |
Jul 27 06:56:27 PM PDT 24 |
26621000 ps |
| T1174 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1502144909 |
|
|
Jul 27 06:56:13 PM PDT 24 |
Jul 27 06:56:26 PM PDT 24 |
30231000 ps |
| T1175 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2223807693 |
|
|
Jul 27 06:55:55 PM PDT 24 |
Jul 27 06:56:11 PM PDT 24 |
21237900 ps |
| T1176 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2192674987 |
|
|
Jul 27 06:55:05 PM PDT 24 |
Jul 27 06:55:21 PM PDT 24 |
40428500 ps |
| T1177 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.187042576 |
|
|
Jul 27 06:56:12 PM PDT 24 |
Jul 27 06:56:25 PM PDT 24 |
152581000 ps |
| T244 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.4092291309 |
|
|
Jul 27 06:55:36 PM PDT 24 |
Jul 27 06:55:52 PM PDT 24 |
123242400 ps |
| T1178 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2899891819 |
|
|
Jul 27 06:54:53 PM PDT 24 |
Jul 27 06:55:07 PM PDT 24 |
23673000 ps |
| T1179 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1774545634 |
|
|
Jul 27 06:56:11 PM PDT 24 |
Jul 27 06:56:25 PM PDT 24 |
49838400 ps |
| T1180 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3223789748 |
|
|
Jul 27 06:55:38 PM PDT 24 |
Jul 27 06:55:58 PM PDT 24 |
295395300 ps |
| T1181 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1983809525 |
|
|
Jul 27 06:54:41 PM PDT 24 |
Jul 27 06:54:54 PM PDT 24 |
195801000 ps |
| T285 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2469059467 |
|
|
Jul 27 06:55:00 PM PDT 24 |
Jul 27 06:55:16 PM PDT 24 |
386690600 ps |
| T1182 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.468175539 |
|
|
Jul 27 06:54:41 PM PDT 24 |
Jul 27 06:54:55 PM PDT 24 |
24103400 ps |
| T1183 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1401182324 |
|
|
Jul 27 06:55:21 PM PDT 24 |
Jul 27 06:55:38 PM PDT 24 |
130294000 ps |
| T1184 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.4029182122 |
|
|
Jul 27 06:55:14 PM PDT 24 |
Jul 27 06:55:27 PM PDT 24 |
26488300 ps |
| T242 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2263631119 |
|
|
Jul 27 06:55:28 PM PDT 24 |
Jul 27 06:55:46 PM PDT 24 |
743804900 ps |
| T1185 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2935389213 |
|
|
Jul 27 06:53:55 PM PDT 24 |
Jul 27 06:54:11 PM PDT 24 |
18549600 ps |
| T336 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1254875355 |
|
|
Jul 27 06:54:57 PM PDT 24 |
Jul 27 07:07:36 PM PDT 24 |
862484600 ps |
| T1186 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2381120721 |
|
|
Jul 27 06:54:50 PM PDT 24 |
Jul 27 06:55:03 PM PDT 24 |
16808200 ps |
| T1187 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.772960337 |
|
|
Jul 27 06:54:31 PM PDT 24 |
Jul 27 06:54:46 PM PDT 24 |
22807000 ps |
| T1188 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3327158098 |
|
|
Jul 27 06:56:14 PM PDT 24 |
Jul 27 06:56:28 PM PDT 24 |
19116600 ps |
| T1189 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.404102713 |
|
|
Jul 27 06:55:29 PM PDT 24 |
Jul 27 06:55:43 PM PDT 24 |
75294800 ps |
| T1190 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.1730916026 |
|
|
Jul 27 06:56:10 PM PDT 24 |
Jul 27 06:56:24 PM PDT 24 |
24056500 ps |
| T338 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3002266262 |
|
|
Jul 27 06:55:37 PM PDT 24 |
Jul 27 07:08:29 PM PDT 24 |
5516271400 ps |
| T1191 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.962825839 |
|
|
Jul 27 06:54:47 PM PDT 24 |
Jul 27 06:55:05 PM PDT 24 |
98698700 ps |
| T245 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2532742084 |
|
|
Jul 27 06:55:46 PM PDT 24 |
Jul 27 06:56:03 PM PDT 24 |
140130700 ps |
| T286 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2041457750 |
|
|
Jul 27 06:55:11 PM PDT 24 |
Jul 27 06:55:31 PM PDT 24 |
176014000 ps |
| T340 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1056957794 |
|
|
Jul 27 06:54:42 PM PDT 24 |
Jul 27 07:02:17 PM PDT 24 |
762656500 ps |
| T1192 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1699682427 |
|
|
Jul 27 06:55:30 PM PDT 24 |
Jul 27 06:55:50 PM PDT 24 |
42806500 ps |
| T1193 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3478154369 |
|
|
Jul 27 06:56:15 PM PDT 24 |
Jul 27 06:56:29 PM PDT 24 |
26499600 ps |
| T1194 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3163780001 |
|
|
Jul 27 06:54:15 PM PDT 24 |
Jul 27 06:54:28 PM PDT 24 |
32662600 ps |
| T263 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3156741850 |
|
|
Jul 27 06:54:40 PM PDT 24 |
Jul 27 06:54:53 PM PDT 24 |
15413100 ps |
| T240 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3142404991 |
|
|
Jul 27 06:55:46 PM PDT 24 |
Jul 27 06:56:06 PM PDT 24 |
90509000 ps |
| T1195 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.906908395 |
|
|
Jul 27 06:54:49 PM PDT 24 |
Jul 27 06:55:06 PM PDT 24 |
35148800 ps |
| T1196 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1237126424 |
|
|
Jul 27 06:55:04 PM PDT 24 |
Jul 27 06:55:18 PM PDT 24 |
86207000 ps |
| T287 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1589010454 |
|
|
Jul 27 06:54:41 PM PDT 24 |
Jul 27 06:55:00 PM PDT 24 |
105366900 ps |
| T1197 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.392422440 |
|
|
Jul 27 06:55:03 PM PDT 24 |
Jul 27 06:55:19 PM PDT 24 |
18099500 ps |
| T288 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1589621890 |
|
|
Jul 27 06:55:06 PM PDT 24 |
Jul 27 06:55:24 PM PDT 24 |
212761200 ps |
| T1198 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.654690911 |
|
|
Jul 27 06:56:12 PM PDT 24 |
Jul 27 06:56:25 PM PDT 24 |
16922500 ps |
| T337 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.2763879772 |
|
|
Jul 27 06:55:46 PM PDT 24 |
Jul 27 07:08:23 PM PDT 24 |
1310658500 ps |
| T1199 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.4093499751 |
|
|
Jul 27 06:56:12 PM PDT 24 |
Jul 27 06:56:26 PM PDT 24 |
67419100 ps |
| T1200 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.22209184 |
|
|
Jul 27 06:54:07 PM PDT 24 |
Jul 27 06:54:22 PM PDT 24 |
29855800 ps |
| T1201 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2432755869 |
|
|
Jul 27 06:55:47 PM PDT 24 |
Jul 27 06:56:04 PM PDT 24 |
40039100 ps |
| T1202 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.407486690 |
|
|
Jul 27 06:55:47 PM PDT 24 |
Jul 27 06:56:00 PM PDT 24 |
63070000 ps |
| T241 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2767755278 |
|
|
Jul 27 06:55:12 PM PDT 24 |
Jul 27 06:55:28 PM PDT 24 |
194046400 ps |
| T289 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1316918614 |
|
|
Jul 27 06:55:00 PM PDT 24 |
Jul 27 06:55:18 PM PDT 24 |
420967200 ps |
| T1203 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3110198304 |
|
|
Jul 27 06:54:01 PM PDT 24 |
Jul 27 06:54:15 PM PDT 24 |
45260400 ps |
| T1204 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2247870446 |
|
|
Jul 27 06:56:12 PM PDT 24 |
Jul 27 06:56:26 PM PDT 24 |
22802500 ps |
| T1205 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2447691948 |
|
|
Jul 27 06:55:01 PM PDT 24 |
Jul 27 06:55:17 PM PDT 24 |
374657500 ps |
| T1206 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3111215304 |
|
|
Jul 27 06:55:37 PM PDT 24 |
Jul 27 06:55:54 PM PDT 24 |
262402200 ps |
| T1207 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.861140505 |
|
|
Jul 27 06:54:49 PM PDT 24 |
Jul 27 06:55:20 PM PDT 24 |
979463000 ps |
| T344 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3457771206 |
|
|
Jul 27 06:54:47 PM PDT 24 |
Jul 27 07:02:29 PM PDT 24 |
3192115300 ps |
| T1208 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2537587105 |
|
|
Jul 27 06:54:23 PM PDT 24 |
Jul 27 06:54:37 PM PDT 24 |
31753900 ps |
| T1209 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.386447477 |
|
|
Jul 27 06:55:05 PM PDT 24 |
Jul 27 06:55:18 PM PDT 24 |
45627300 ps |
| T246 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.378329582 |
|
|
Jul 27 06:54:03 PM PDT 24 |
Jul 27 06:54:22 PM PDT 24 |
58363400 ps |
| T1210 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2773367380 |
|
|
Jul 27 06:55:30 PM PDT 24 |
Jul 27 06:55:47 PM PDT 24 |
324180200 ps |
| T339 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2056068114 |
|
|
Jul 27 06:55:29 PM PDT 24 |
Jul 27 07:10:24 PM PDT 24 |
679756100 ps |
| T1211 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2318557588 |
|
|
Jul 27 06:55:48 PM PDT 24 |
Jul 27 06:56:02 PM PDT 24 |
15074800 ps |
| T1212 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.760908500 |
|
|
Jul 27 06:56:12 PM PDT 24 |
Jul 27 06:56:25 PM PDT 24 |
17066900 ps |
| T1213 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.383184089 |
|
|
Jul 27 06:55:21 PM PDT 24 |
Jul 27 06:55:35 PM PDT 24 |
20066100 ps |
| T1214 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3581494508 |
|
|
Jul 27 06:54:51 PM PDT 24 |
Jul 27 06:55:40 PM PDT 24 |
1545121200 ps |
| T260 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.614177905 |
|
|
Jul 27 06:54:51 PM PDT 24 |
Jul 27 06:55:05 PM PDT 24 |
67238300 ps |
| T1215 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.581290231 |
|
|
Jul 27 06:55:46 PM PDT 24 |
Jul 27 06:56:02 PM PDT 24 |
53315200 ps |
| T1216 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.655765190 |
|
|
Jul 27 06:55:56 PM PDT 24 |
Jul 27 06:56:10 PM PDT 24 |
16980000 ps |
| T1217 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.965944386 |
|
|
Jul 27 06:55:56 PM PDT 24 |
Jul 27 06:56:09 PM PDT 24 |
17128500 ps |
| T1218 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3659555890 |
|
|
Jul 27 06:55:01 PM PDT 24 |
Jul 27 06:55:17 PM PDT 24 |
12698000 ps |
| T1219 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2232488782 |
|
|
Jul 27 06:53:55 PM PDT 24 |
Jul 27 06:54:09 PM PDT 24 |
16358300 ps |
| T1220 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.407260487 |
|
|
Jul 27 06:54:40 PM PDT 24 |
Jul 27 06:54:57 PM PDT 24 |
319826200 ps |
| T1221 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2532277304 |
|
|
Jul 27 06:55:46 PM PDT 24 |
Jul 27 06:56:00 PM PDT 24 |
12077900 ps |
| T1222 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2923815310 |
|
|
Jul 27 06:53:59 PM PDT 24 |
Jul 27 06:54:24 PM PDT 24 |
43395500 ps |
| T1223 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.4004679678 |
|
|
Jul 27 06:54:33 PM PDT 24 |
Jul 27 06:54:53 PM PDT 24 |
58812800 ps |
| T348 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.716497001 |
|
|
Jul 27 06:54:01 PM PDT 24 |
Jul 27 07:09:00 PM PDT 24 |
1339719100 ps |
| T1224 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1492560700 |
|
|
Jul 27 06:53:54 PM PDT 24 |
Jul 27 06:54:10 PM PDT 24 |
50784900 ps |
| T347 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2422406236 |
|
|
Jul 27 06:53:54 PM PDT 24 |
Jul 27 07:09:04 PM PDT 24 |
677716800 ps |
| T1225 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2987259844 |
|
|
Jul 27 06:55:54 PM PDT 24 |
Jul 27 06:56:12 PM PDT 24 |
259788400 ps |
| T1226 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3090848679 |
|
|
Jul 27 06:55:30 PM PDT 24 |
Jul 27 06:55:48 PM PDT 24 |
284065300 ps |
| T341 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1611534573 |
|
|
Jul 27 06:55:21 PM PDT 24 |
Jul 27 07:03:01 PM PDT 24 |
3018467900 ps |
| T343 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3407073843 |
|
|
Jul 27 06:55:30 PM PDT 24 |
Jul 27 07:08:22 PM PDT 24 |
972596700 ps |
| T1227 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1276728869 |
|
|
Jul 27 06:56:08 PM PDT 24 |
Jul 27 06:56:21 PM PDT 24 |
17274900 ps |
| T1228 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.3508012842 |
|
|
Jul 27 06:55:56 PM PDT 24 |
Jul 27 06:56:10 PM PDT 24 |
28858800 ps |
| T1229 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.202830555 |
|
|
Jul 27 06:54:55 PM PDT 24 |
Jul 27 06:55:10 PM PDT 24 |
92884600 ps |
| T290 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.290641638 |
|
|
Jul 27 06:55:39 PM PDT 24 |
Jul 27 06:55:57 PM PDT 24 |
118352100 ps |
| T1230 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.616983343 |
|
|
Jul 27 06:54:41 PM PDT 24 |
Jul 27 06:54:54 PM PDT 24 |
27148500 ps |
| T342 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.306099644 |
|
|
Jul 27 06:55:07 PM PDT 24 |
Jul 27 07:02:48 PM PDT 24 |
361504600 ps |
| T1231 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3927464905 |
|
|
Jul 27 06:54:40 PM PDT 24 |
Jul 27 06:54:54 PM PDT 24 |
46641800 ps |
| T1232 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.7829343 |
|
|
Jul 27 06:55:34 PM PDT 24 |
Jul 27 06:55:49 PM PDT 24 |
168103800 ps |
| T1233 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2492934307 |
|
|
Jul 27 06:55:38 PM PDT 24 |
Jul 27 06:55:55 PM PDT 24 |
29903700 ps |
| T1234 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2966464274 |
|
|
Jul 27 06:55:58 PM PDT 24 |
Jul 27 06:56:17 PM PDT 24 |
94408600 ps |
| T349 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3869875284 |
|
|
Jul 27 06:55:29 PM PDT 24 |
Jul 27 07:03:08 PM PDT 24 |
358648400 ps |
| T1235 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3264354200 |
|
|
Jul 27 06:55:14 PM PDT 24 |
Jul 27 06:55:29 PM PDT 24 |
14262800 ps |
| T1236 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3019610021 |
|
|
Jul 27 06:55:02 PM PDT 24 |
Jul 27 06:55:16 PM PDT 24 |
15963100 ps |
| T1237 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.1381219345 |
|
|
Jul 27 06:54:42 PM PDT 24 |
Jul 27 06:55:08 PM PDT 24 |
155992300 ps |
| T345 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2457937765 |
|
|
Jul 27 06:55:13 PM PDT 24 |
Jul 27 07:02:49 PM PDT 24 |
2773789900 ps |
| T1238 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.343493273 |
|
|
Jul 27 06:55:21 PM PDT 24 |
Jul 27 06:55:37 PM PDT 24 |
33473400 ps |
| T1239 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1675662443 |
|
|
Jul 27 06:55:59 PM PDT 24 |
Jul 27 06:56:13 PM PDT 24 |
45722500 ps |
| T1240 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3562154115 |
|
|
Jul 27 06:54:22 PM PDT 24 |
Jul 27 06:54:35 PM PDT 24 |
14469300 ps |
| T247 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2913810753 |
|
|
Jul 27 06:55:45 PM PDT 24 |
Jul 27 07:08:24 PM PDT 24 |
1650231200 ps |
| T1241 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2825226130 |
|
|
Jul 27 06:55:55 PM PDT 24 |
Jul 27 06:56:13 PM PDT 24 |
81412100 ps |
| T1242 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1247636403 |
|
|
Jul 27 06:55:36 PM PDT 24 |
Jul 27 06:55:55 PM PDT 24 |
458704600 ps |
| T1243 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2496168928 |
|
|
Jul 27 06:54:47 PM PDT 24 |
Jul 27 06:55:33 PM PDT 24 |
42453100 ps |
| T1244 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3070189057 |
|
|
Jul 27 06:55:29 PM PDT 24 |
Jul 27 06:55:49 PM PDT 24 |
54838900 ps |
| T1245 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.999260271 |
|
|
Jul 27 06:55:03 PM PDT 24 |
Jul 27 06:55:20 PM PDT 24 |
36460800 ps |
| T1246 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.4136260744 |
|
|
Jul 27 06:54:09 PM PDT 24 |
Jul 27 06:55:21 PM PDT 24 |
2391094200 ps |
| T1247 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.4220139393 |
|
|
Jul 27 06:54:08 PM PDT 24 |
Jul 27 06:54:28 PM PDT 24 |
198018400 ps |
| T1248 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1317634758 |
|
|
Jul 27 06:55:29 PM PDT 24 |
Jul 27 06:55:45 PM PDT 24 |
35513700 ps |
| T1249 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1964396738 |
|
|
Jul 27 06:56:12 PM PDT 24 |
Jul 27 06:56:26 PM PDT 24 |
15785300 ps |
| T1250 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.4113960806 |
|
|
Jul 27 06:56:13 PM PDT 24 |
Jul 27 06:56:26 PM PDT 24 |
16018900 ps |
| T1251 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.373025785 |
|
|
Jul 27 06:54:30 PM PDT 24 |
Jul 27 07:02:04 PM PDT 24 |
385668000 ps |
| T264 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2873528402 |
|
|
Jul 27 06:54:06 PM PDT 24 |
Jul 27 06:54:20 PM PDT 24 |
50656300 ps |