Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	328246	1		T1	2		T2	1		T3	1
all_values[1]	328246	1		T1	2		T2	1		T3	1
all_values[2]	328246	1		T1	2		T2	1		T3	1
all_values[3]	328246	1		T1	2		T2	1		T3	1
all_values[4]	328246	1		T1	2		T2	1		T3	1
all_values[5]	328246	1		T1	2		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	662833	1		T1	12		T2	6		T3	6
auto[1]	1306643	1		T4	96756		T19	6512		T8	12632

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	961668	1		T1	6		T2	4		T3	4
auto[1]	1007808	1		T1	6		T2	2		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	328064	1		T1	2		T2	1		T3	1
all_values[0]	auto[1]	auto[1]	182	1		T273	5		T274	3		T348	2
all_values[1]	auto[0]	auto[1]	328090	1		T1	2		T2	1		T3	1
all_values[1]	auto[1]	auto[1]	156	1		T273	4		T274	5		T348	1
all_values[2]	auto[0]	auto[0]	1624	1		T1	2		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	49	1		T273	1		T274	1		T348	1
all_values[2]	auto[1]	auto[0]	326517	1		T4	24189		T19	1628		T8	3158
all_values[2]	auto[1]	auto[1]	56	1		T273	1		T274	1		T350	2
all_values[3]	auto[0]	auto[0]	1623	1		T1	2		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	37	1		T273	1		T274	1		T348	2
all_values[3]	auto[1]	auto[0]	88635	1		T19	1628		T8	1579		T22	1796
all_values[3]	auto[1]	auto[1]	237951	1		T4	24189		T8	1579		T22	3592
all_values[4]	auto[0]	auto[0]	1153	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	526	1		T1	1		T7	1		T45	1
all_values[4]	auto[1]	auto[0]	214047	1		T4	23221		T19	1		T8	1579
all_values[4]	auto[1]	auto[1]	112520	1		T4	968		T19	1627		T8	1579
all_values[5]	auto[0]	auto[0]	1565	1		T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	102	1		T1	1		T36	1		T37	1
all_values[5]	auto[1]	auto[0]	326504	1		T4	24189		T19	1628		T8	3158
all_values[5]	auto[1]	auto[1]	75	1		T273	4		T274	3		T350	1