Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	236994	1		T1	146		T3	6		T4	545
auto[FlashEraseBank]	263004	1		T1	180		T3	6		T4	423

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	256893	1		T1	179		T3	11		T4	968
auto[FlashOpProgram]	224435	1		T1	147		T3	1		T19	1627
auto[FlashOpErase]	14670	1		T7	100		T21	6		T68	231
auto[FlashOpInvalid]	4000	1		T7	200		T92	200		T49	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	256893	1		T1	179		T3	11		T4	968
op[FlashOpProgram]	224435	1		T1	147		T3	1		T19	1627
op[FlashOpErase]	14670	1		T7	100		T21	6		T68	231
read_erase_read	550	1		T21	1		T28	15		T66	14
read_prog_read	853	1		T3	1		T26	1		T45	8

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	366937	1		T1	130		T3	1		T4	939
auto[FlashPartInfo]	129247	1		T1	174		T3	11		T19	178
auto[FlashPartInfo1]	865	1		T4	13		T7	6		T45	5
auto[FlashPartInfo2]	2949	1		T1	22		T4	16		T19	4

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	191497	1		T1	59		T3	1		T4	939
auto[FlashPartData]	auto[FlashOpProgram]	167938	1		T1	71		T19	1445		T20	1141
auto[FlashPartData]	auto[FlashOpErase]	3586	1		T7	97		T28	12		T92	100
auto[FlashPartData]	auto[FlashOpInvalid]	3916	1		T7	194		T92	200		T49	198
auto[FlashPartInfo]	auto[FlashOpRead]	62749	1		T1	106		T3	10		T7	2
auto[FlashPartInfo]	auto[FlashOpProgram]	55379	1		T1	68		T3	1		T19	178
auto[FlashPartInfo]	auto[FlashOpErase]	11049	1		T7	1		T21	6		T68	231
auto[FlashPartInfo]	auto[FlashOpInvalid]	70	1		T7	2		T49	2		T167	2
auto[FlashPartInfo1]	auto[FlashOpRead]	691	1		T4	13		T7	2		T45	5
auto[FlashPartInfo1]	auto[FlashOpProgram]	166	1		T7	1		T102	1		T146	1
auto[FlashPartInfo1]	auto[FlashOpErase]	4	1		T7	1		T146	1		T148	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T7	2		T146	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1956	1		T1	14		T4	16		T7	2
auto[FlashPartInfo2]	auto[FlashOpProgram]	952	1		T1	8		T19	4		T20	5
auto[FlashPartInfo2]	auto[FlashOpErase]	31	1		T7	1		T66	2		T84	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T7	2		T146	2		T426	2