Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	2	30	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	2	30	93.75	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28819	1		T7	400		T68	488		T92	400
auto[1]	45	1		T27	1		T361	3		T362	1
auto[2]	73	1		T207	1		T163	1		T361	2
auto[3]	234	1		T3	1		T26	1		T28	21

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7301	1		T7	100		T68	122		T28	5
evic_idx[1]	7287	1		T3	1		T7	100		T26	1
evic_idx[2]	7299	1		T7	100		T68	122		T28	7
evic_idx[3]	7284	1		T7	100		T68	122		T28	5

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28287	1		T7	400		T68	488		T28	21
evic_op[2]	295	1		T3	1		T26	1		T46	2

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	2	30	93.75	2

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[1]]	[evic_op[2]]	[auto[1] - auto[2]]	--	--	2

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7007	1		T7	100		T68	122		T92	100
evic_idx[0]	evic_op[1]	auto[1]	7	1		T296	3		T305	1		T363	1
evic_idx[0]	evic_op[1]	auto[2]	6	1		T361	1		T364	2		T365	2
evic_idx[0]	evic_op[1]	auto[3]	57	1		T28	5		T66	5		T361	1
evic_idx[0]	evic_op[2]	auto[0]	61	1		T31	1		T232	4		T82	1
evic_idx[0]	evic_op[2]	auto[1]	2	1		T218	1		T366	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	4	1		T163	1		T362	1		T367	1
evic_idx[0]	evic_op[2]	auto[3]	9	1		T368	1		T220	1		T369	1
evic_idx[1]	evic_op[1]	auto[0]	7009	1		T7	100		T68	122		T92	100
evic_idx[1]	evic_op[1]	auto[1]	8	1		T361	1		T370	1		T296	1
evic_idx[1]	evic_op[1]	auto[2]	5	1		T364	2		T365	2		T371	1
evic_idx[1]	evic_op[1]	auto[3]	50	1		T28	4		T66	5		T244	6
evic_idx[1]	evic_op[2]	auto[0]	57	1		T31	1		T232	4		T235	1
evic_idx[1]	evic_op[2]	auto[3]	11	1		T3	1		T26	1		T46	2
evic_idx[2]	evic_op[1]	auto[0]	7012	1		T7	100		T68	122		T92	100
evic_idx[2]	evic_op[1]	auto[1]	11	1		T361	1		T370	1		T296	1
evic_idx[2]	evic_op[1]	auto[2]	8	1		T364	2		T365	5		T371	1
evic_idx[2]	evic_op[1]	auto[3]	40	1		T28	7		T66	3		T361	1
evic_idx[2]	evic_op[2]	auto[0]	62	1		T31	1		T232	4		T235	1
evic_idx[2]	evic_op[2]	auto[1]	3	1		T362	1		T372	1		T373	1
evic_idx[2]	evic_op[2]	auto[2]	2	1		T207	1		T374	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	14	1		T207	1		T209	1		T375	1
evic_idx[3]	evic_op[1]	auto[0]	7005	1		T7	100		T68	122		T92	100
evic_idx[3]	evic_op[1]	auto[1]	11	1		T361	1		T370	1		T296	2
evic_idx[3]	evic_op[1]	auto[2]	5	1		T361	1		T364	2		T365	1
evic_idx[3]	evic_op[1]	auto[3]	46	1		T28	5		T66	4		T361	1
evic_idx[3]	evic_op[2]	auto[0]	57	1		T31	1		T232	4		T235	1
evic_idx[3]	evic_op[2]	auto[1]	3	1		T27	1		T376	1		T366	1
evic_idx[3]	evic_op[2]	auto[2]	3	1		T374	1		T377	2		-	-
evic_idx[3]	evic_op[2]	auto[3]	7	1		T378	1		T156	1		T379	1