Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	16921	1		T4	9678		T355	2374		T356	2562
rd_lvl[2]	29037	1		T4	5798		T73	1542		T355	1169
rd_lvl[3]	21784	1		T73	1947		T294	900		T295	758
rd_lvl[4]	47386	1		T73	668		T294	695		T295	2535
rd_lvl[5]	13143	1		T73	1376		T294	66		T295	140
rd_lvl[6]	18948	1		T22	3044		T73	1184		T294	201
rd_lvl[7]	12271	1		T22	548		T73	672		T294	3
rd_lvl[8]	14499	1		T73	666		T294	1		T295	955
rd_lvl[9]	7021	1		T4	1		T73	665		T219	404
rd_lvl[10]	9959	1		T8	1191		T219	1271		T161	1037
rd_lvl[11]	4031	1		T4	1		T8	388		T355	43
rd_lvl[12]	10323	1		T292	461		T357	1445		T358	1077
rd_lvl[13]	3805	1		T229	458		T294	201		T292	1348
rd_lvl[14]	5755	1		T229	1142		T33	356		T34	53
rd_lvl[15]	2234	1		T33	186		T34	21		T35	202