Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	328246	1		T1	2		T2	1		T3	1
all_pins[1]	328246	1		T1	2		T2	1		T3	1
all_pins[2]	328246	1		T1	2		T2	1		T3	1
all_pins[3]	328246	1		T1	2		T2	1		T3	1
all_pins[4]	328246	1		T1	2		T2	1		T3	1
all_pins[5]	328246	1		T1	2		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1629794	1		T1	12		T2	6		T3	6
values[0x1]	339682	1		T4	16939		T19	1627		T8	3158
transitions[0x0=>0x1]	308545	1		T4	15478		T19	1627		T8	3158
transitions[0x1=>0x0]	308529	1		T4	15478		T19	1627		T8	3158

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	328064	1		T1	2		T2	1		T3	1
all_pins[0]	values[0x1]	182	1		T273	5		T274	3		T348	2
all_pins[0]	transitions[0x0=>0x1]	96	1		T273	3		T274	1		T348	2
all_pins[0]	transitions[0x1=>0x0]	70	1		T273	2		T274	3		T348	1
all_pins[1]	values[0x0]	328090	1		T1	2		T2	1		T3	1
all_pins[1]	values[0x1]	156	1		T273	4		T274	5		T348	1
all_pins[1]	transitions[0x0=>0x1]	132	1		T273	3		T274	4		T348	1
all_pins[1]	transitions[0x1=>0x0]	2131	1		T33	5		T34	1		T35	94
all_pins[2]	values[0x0]	326091	1		T1	2		T2	1		T3	1
all_pins[2]	values[0x1]	2155	1		T33	5		T34	1		T35	94
all_pins[2]	transitions[0x0=>0x1]	38	1		T274	1		T380	1		T352	2
all_pins[2]	transitions[0x1=>0x0]	217170	1		T4	15478		T8	1579		T22	3592
all_pins[3]	values[0x0]	108959	1		T1	2		T2	1		T3	1
all_pins[3]	values[0x1]	219287	1		T4	15478		T8	1579		T22	3592
all_pins[3]	transitions[0x0=>0x1]	190454	1		T4	14017		T8	1579		T22	3592
all_pins[3]	transitions[0x1=>0x0]	88994	1		T19	1627		T8	1579		T22	1796
all_pins[4]	values[0x0]	210419	1		T1	2		T2	1		T3	1
all_pins[4]	values[0x1]	117827	1		T4	1461		T19	1627		T8	1579
all_pins[4]	transitions[0x0=>0x1]	117804	1		T4	1461		T19	1627		T8	1579
all_pins[4]	transitions[0x1=>0x0]	52	1		T273	3		T274	1		T350	1
all_pins[5]	values[0x0]	328171	1		T1	2		T2	1		T3	1
all_pins[5]	values[0x1]	75	1		T273	4		T274	3		T350	1
all_pins[5]	transitions[0x0=>0x1]	21	1		T273	1		T274	1		T381	1
all_pins[5]	transitions[0x1=>0x0]	112	1		T273	1		T274	2		T348	1