Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1		T273	7		T274	7		T348	4
all_values[1]	269	1		T273	7		T274	7		T348	4
all_values[2]	269	1		T273	7		T274	7		T348	4
all_values[3]	269	1		T273	7		T274	7		T348	4
all_values[4]	269	1		T273	7		T274	7		T348	4
all_values[5]	269	1		T273	7		T274	7		T348	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	843	1		T273	20		T274	11		T348	19
auto[1]	771	1		T273	22		T274	31		T348	5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	524	1		T273	14		T274	13		T348	8
auto[1]	1090	1		T273	28		T274	29		T348	16

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	962	1		T273	27		T274	24		T348	13
auto[1]	652	1		T273	15		T274	18		T348	11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	75	1		T273	4		T274	1		T348	1
all_values[0]	auto[0]	auto[1]	auto[1]	85	1		T273	2		T274	4		T348	2
all_values[0]	auto[1]	auto[0]	auto[1]	50	1		T273	1		T348	1		T349	1
all_values[0]	auto[1]	auto[1]	auto[1]	59	1		T274	2		T349	1		T350	4
all_values[1]	auto[0]	auto[0]	auto[1]	92	1		T273	2		T348	2		T350	3
all_values[1]	auto[0]	auto[1]	auto[1]	64	1		T273	2		T274	2		T349	2
all_values[1]	auto[1]	auto[0]	auto[1]	59	1		T273	1		T274	2		T348	1
all_values[1]	auto[1]	auto[1]	auto[1]	54	1		T273	2		T274	3		T348	1
all_values[2]	auto[0]	auto[0]	auto[0]	85	1		T273	1		T274	1		T348	3
all_values[2]	auto[0]	auto[1]	auto[0]	79	1		T273	4		T274	4		T349	1
all_values[2]	auto[1]	auto[0]	auto[1]	56	1		T273	1		T348	1		T349	1
all_values[2]	auto[1]	auto[1]	auto[1]	49	1		T273	1		T274	2		T350	2
all_values[3]	auto[0]	auto[0]	auto[0]	88	1		T273	3		T274	2		T348	1
all_values[3]	auto[0]	auto[1]	auto[0]	74	1		T273	2		T274	2		T350	1
all_values[3]	auto[1]	auto[0]	auto[1]	51	1		T273	1		T274	2		T348	3
all_values[3]	auto[1]	auto[1]	auto[1]	56	1		T273	1		T274	1		T349	2
all_values[4]	auto[0]	auto[0]	auto[0]	63	1		T273	2		T348	2		T349	4
all_values[4]	auto[0]	auto[0]	auto[1]	24	1		T274	1		T350	1		T351	1
all_values[4]	auto[0]	auto[1]	auto[0]	48	1		T273	1		T274	1		T351	3
all_values[4]	auto[0]	auto[1]	auto[1]	24	1		T274	1		T352	1		T353	2
all_values[4]	auto[1]	auto[0]	auto[1]	65	1		T273	1		T274	2		T348	2
all_values[4]	auto[1]	auto[1]	auto[1]	45	1		T273	3		T274	2		T350	2
all_values[5]	auto[0]	auto[0]	auto[0]	43	1		T273	1		T349	1		T350	1
all_values[5]	auto[0]	auto[0]	auto[1]	34	1		T273	1		T351	1		T354	1
all_values[5]	auto[0]	auto[1]	auto[0]	44	1		T274	3		T348	2		T349	3
all_values[5]	auto[0]	auto[1]	auto[1]	40	1		T273	2		T274	2		T351	1
all_values[5]	auto[1]	auto[0]	auto[1]	58	1		T273	1		T348	2		T350	1
all_values[5]	auto[1]	auto[1]	auto[1]	50	1		T273	2		T274	2		T350	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal