| T371 |
/workspace/coverage/default/10.flash_ctrl_re_evict.3484216010 |
|
|
Jul 29 06:01:25 PM PDT 24 |
Jul 29 06:01:58 PM PDT 24 |
127535900 ps |
| T1090 |
/workspace/coverage/default/1.flash_ctrl_smoke.1969015812 |
|
|
Jul 29 05:56:18 PM PDT 24 |
Jul 29 05:58:24 PM PDT 24 |
21804300 ps |
| T1091 |
/workspace/coverage/default/45.flash_ctrl_hw_sec_otp.1562905495 |
|
|
Jul 29 06:06:53 PM PDT 24 |
Jul 29 06:10:38 PM PDT 24 |
10750879400 ps |
| T1092 |
/workspace/coverage/default/32.flash_ctrl_smoke.262044868 |
|
|
Jul 29 06:05:36 PM PDT 24 |
Jul 29 06:07:40 PM PDT 24 |
27194200 ps |
| T128 |
/workspace/coverage/default/4.flash_ctrl_phy_arb_redun.4037853167 |
|
|
Jul 29 05:59:04 PM PDT 24 |
Jul 29 05:59:22 PM PDT 24 |
805421500 ps |
| T169 |
/workspace/coverage/default/1.flash_ctrl_mid_op_rst.548240020 |
|
|
Jul 29 05:56:37 PM PDT 24 |
Jul 29 05:57:50 PM PDT 24 |
1713684300 ps |
| T1093 |
/workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.2735790614 |
|
|
Jul 29 06:00:49 PM PDT 24 |
Jul 29 06:01:03 PM PDT 24 |
25498300 ps |
| T1094 |
/workspace/coverage/default/42.flash_ctrl_disable.1308170684 |
|
|
Jul 29 06:06:39 PM PDT 24 |
Jul 29 06:07:00 PM PDT 24 |
10377700 ps |
| T1095 |
/workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.1958226296 |
|
|
Jul 29 06:00:33 PM PDT 24 |
Jul 29 06:01:05 PM PDT 24 |
68480600 ps |
| T1096 |
/workspace/coverage/default/46.flash_ctrl_connect.3388720120 |
|
|
Jul 29 06:06:55 PM PDT 24 |
Jul 29 06:07:09 PM PDT 24 |
47866600 ps |
| T1097 |
/workspace/coverage/default/7.flash_ctrl_rw_evict.1593345410 |
|
|
Jul 29 06:00:20 PM PDT 24 |
Jul 29 06:00:51 PM PDT 24 |
38176600 ps |
| T1098 |
/workspace/coverage/default/0.flash_ctrl_serr_counter.1157126537 |
|
|
Jul 29 05:55:54 PM PDT 24 |
Jul 29 05:57:09 PM PDT 24 |
2554314600 ps |
| T1099 |
/workspace/coverage/default/3.flash_ctrl_erase_suspend.278847901 |
|
|
Jul 29 05:57:56 PM PDT 24 |
Jul 29 06:06:36 PM PDT 24 |
10790115700 ps |
| T1100 |
/workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.1768443101 |
|
|
Jul 29 05:59:54 PM PDT 24 |
Jul 29 06:00:26 PM PDT 24 |
30501000 ps |
| T15 |
/workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.3895377570 |
|
|
Jul 29 05:59:02 PM PDT 24 |
Jul 29 05:59:16 PM PDT 24 |
24673700 ps |
| T1101 |
/workspace/coverage/default/15.flash_ctrl_alert_test.2580174539 |
|
|
Jul 29 06:03:08 PM PDT 24 |
Jul 29 06:03:22 PM PDT 24 |
34208900 ps |
| T1102 |
/workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.2943734579 |
|
|
Jul 29 06:02:20 PM PDT 24 |
Jul 29 06:07:35 PM PDT 24 |
48157633400 ps |
| T51 |
/workspace/coverage/default/2.flash_ctrl_access_after_disable.532551421 |
|
|
Jul 29 05:57:42 PM PDT 24 |
Jul 29 05:57:56 PM PDT 24 |
14223100 ps |
| T1103 |
/workspace/coverage/default/31.flash_ctrl_alert_test.3013259172 |
|
|
Jul 29 06:05:37 PM PDT 24 |
Jul 29 06:05:51 PM PDT 24 |
33721000 ps |
| T1104 |
/workspace/coverage/default/4.flash_ctrl_rw_derr.2965557609 |
|
|
Jul 29 05:58:43 PM PDT 24 |
Jul 29 06:01:19 PM PDT 24 |
5125305900 ps |
| T1105 |
/workspace/coverage/default/3.flash_ctrl_lcmgr_intg.3330844273 |
|
|
Jul 29 05:58:27 PM PDT 24 |
Jul 29 05:58:41 PM PDT 24 |
51032400 ps |
| T1106 |
/workspace/coverage/default/14.flash_ctrl_smoke.551243437 |
|
|
Jul 29 06:02:34 PM PDT 24 |
Jul 29 06:03:49 PM PDT 24 |
25497400 ps |
| T175 |
/workspace/coverage/default/2.flash_ctrl_mid_op_rst.1100813355 |
|
|
Jul 29 05:57:22 PM PDT 24 |
Jul 29 05:58:31 PM PDT 24 |
1645280700 ps |
| T1107 |
/workspace/coverage/default/0.flash_ctrl_host_addr_infection.2448668864 |
|
|
Jul 29 05:56:18 PM PDT 24 |
Jul 29 05:56:47 PM PDT 24 |
64234700 ps |
| T1108 |
/workspace/coverage/default/1.flash_ctrl_fetch_code.2944118094 |
|
|
Jul 29 05:56:32 PM PDT 24 |
Jul 29 05:56:58 PM PDT 24 |
720454700 ps |
| T1109 |
/workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.1567396117 |
|
|
Jul 29 06:03:52 PM PDT 24 |
Jul 29 06:04:06 PM PDT 24 |
15293600 ps |
| T1110 |
/workspace/coverage/default/47.flash_ctrl_smoke.3614398421 |
|
|
Jul 29 06:07:01 PM PDT 24 |
Jul 29 06:10:20 PM PDT 24 |
716114600 ps |
| T1111 |
/workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.3383152611 |
|
|
Jul 29 06:03:05 PM PDT 24 |
Jul 29 06:04:36 PM PDT 24 |
10044699400 ps |
| T1112 |
/workspace/coverage/default/12.flash_ctrl_hw_rma_reset.2670765570 |
|
|
Jul 29 06:01:51 PM PDT 24 |
Jul 29 06:17:38 PM PDT 24 |
160174368500 ps |
| T1113 |
/workspace/coverage/default/29.flash_ctrl_disable.593843955 |
|
|
Jul 29 06:05:18 PM PDT 24 |
Jul 29 06:05:41 PM PDT 24 |
10732200 ps |
| T373 |
/workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.3239651893 |
|
|
Jul 29 06:02:56 PM PDT 24 |
Jul 29 06:03:27 PM PDT 24 |
62692300 ps |
| T1114 |
/workspace/coverage/default/4.flash_ctrl_full_mem_access.1655913891 |
|
|
Jul 29 05:58:37 PM PDT 24 |
Jul 29 06:41:42 PM PDT 24 |
183720935500 ps |
| T1115 |
/workspace/coverage/default/18.flash_ctrl_prog_reset.2613798121 |
|
|
Jul 29 06:03:47 PM PDT 24 |
Jul 29 06:04:01 PM PDT 24 |
20839000 ps |
| T1116 |
/workspace/coverage/default/13.flash_ctrl_sec_info_access.3256241578 |
|
|
Jul 29 06:02:24 PM PDT 24 |
Jul 29 06:03:36 PM PDT 24 |
2624094400 ps |
| T1117 |
/workspace/coverage/default/73.flash_ctrl_otp_reset.3837817527 |
|
|
Jul 29 06:07:32 PM PDT 24 |
Jul 29 06:09:27 PM PDT 24 |
54353600 ps |
| T198 |
/workspace/coverage/default/2.flash_ctrl_rma_err.2886464540 |
|
|
Jul 29 05:57:46 PM PDT 24 |
Jul 29 06:13:39 PM PDT 24 |
91454637300 ps |
| T1118 |
/workspace/coverage/default/69.flash_ctrl_otp_reset.3474732665 |
|
|
Jul 29 06:07:31 PM PDT 24 |
Jul 29 06:09:23 PM PDT 24 |
42120300 ps |
| T1119 |
/workspace/coverage/default/8.flash_ctrl_invalid_op.19351956 |
|
|
Jul 29 06:00:41 PM PDT 24 |
Jul 29 06:01:56 PM PDT 24 |
2168564000 ps |
| T367 |
/workspace/coverage/default/2.flash_ctrl_rw_evict.3196127361 |
|
|
Jul 29 05:57:37 PM PDT 24 |
Jul 29 05:58:09 PM PDT 24 |
32886000 ps |
| T1120 |
/workspace/coverage/default/8.flash_ctrl_wo.324588272 |
|
|
Jul 29 06:00:40 PM PDT 24 |
Jul 29 06:04:15 PM PDT 24 |
17399939600 ps |
| T1121 |
/workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.4214985117 |
|
|
Jul 29 06:05:19 PM PDT 24 |
Jul 29 06:10:09 PM PDT 24 |
45257831200 ps |
| T1122 |
/workspace/coverage/default/15.flash_ctrl_phy_arb.3905963085 |
|
|
Jul 29 06:02:46 PM PDT 24 |
Jul 29 06:07:29 PM PDT 24 |
205752400 ps |
| T1123 |
/workspace/coverage/default/9.flash_ctrl_connect.1337361639 |
|
|
Jul 29 06:01:13 PM PDT 24 |
Jul 29 06:01:29 PM PDT 24 |
13459000 ps |
| T228 |
/workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.1000728415 |
|
|
Jul 29 05:57:03 PM PDT 24 |
Jul 29 05:57:17 PM PDT 24 |
156672400 ps |
| T1124 |
/workspace/coverage/default/9.flash_ctrl_rw_evict.4053705896 |
|
|
Jul 29 06:01:08 PM PDT 24 |
Jul 29 06:01:40 PM PDT 24 |
28443600 ps |
| T1125 |
/workspace/coverage/default/14.flash_ctrl_wo.1038824196 |
|
|
Jul 29 06:02:33 PM PDT 24 |
Jul 29 06:05:16 PM PDT 24 |
8041384500 ps |
| T1126 |
/workspace/coverage/default/10.flash_ctrl_smoke.2749617034 |
|
|
Jul 29 06:01:23 PM PDT 24 |
Jul 29 06:02:42 PM PDT 24 |
143614000 ps |
| T1127 |
/workspace/coverage/default/37.flash_ctrl_connect.3586641150 |
|
|
Jul 29 06:06:14 PM PDT 24 |
Jul 29 06:06:28 PM PDT 24 |
15585900 ps |
| T1128 |
/workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.3873200465 |
|
|
Jul 29 06:04:02 PM PDT 24 |
Jul 29 06:04:33 PM PDT 24 |
28776300 ps |
| T1129 |
/workspace/coverage/default/40.flash_ctrl_otp_reset.3128676103 |
|
|
Jul 29 06:06:30 PM PDT 24 |
Jul 29 06:08:22 PM PDT 24 |
146359800 ps |
| T1130 |
/workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.341369944 |
|
|
Jul 29 06:05:08 PM PDT 24 |
Jul 29 06:05:41 PM PDT 24 |
56528000 ps |
| T1131 |
/workspace/coverage/default/15.flash_ctrl_mp_regions.2938713511 |
|
|
Jul 29 06:02:51 PM PDT 24 |
Jul 29 06:05:23 PM PDT 24 |
12231481400 ps |
| T1132 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3931387529 |
|
|
Jul 29 05:38:47 PM PDT 24 |
Jul 29 05:39:03 PM PDT 24 |
17539700 ps |
| T273 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3516218846 |
|
|
Jul 29 05:39:45 PM PDT 24 |
Jul 29 05:39:58 PM PDT 24 |
17226100 ps |
| T74 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.668148870 |
|
|
Jul 29 05:39:12 PM PDT 24 |
Jul 29 05:46:47 PM PDT 24 |
743853200 ps |
| T75 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.278650811 |
|
|
Jul 29 05:39:05 PM PDT 24 |
Jul 29 05:39:20 PM PDT 24 |
160580300 ps |
| T76 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.779654223 |
|
|
Jul 29 05:39:14 PM PDT 24 |
Jul 29 05:39:32 PM PDT 24 |
87005100 ps |
| T114 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3261096347 |
|
|
Jul 29 05:38:52 PM PDT 24 |
Jul 29 05:53:49 PM PDT 24 |
1274079300 ps |
| T115 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.4071693459 |
|
|
Jul 29 05:39:14 PM PDT 24 |
Jul 29 05:39:31 PM PDT 24 |
70214600 ps |
| T117 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2911882229 |
|
|
Jul 29 05:38:56 PM PDT 24 |
Jul 29 05:39:42 PM PDT 24 |
105123500 ps |
| T1133 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1401767152 |
|
|
Jul 29 05:38:41 PM PDT 24 |
Jul 29 05:38:58 PM PDT 24 |
34914400 ps |
| T274 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1251529752 |
|
|
Jul 29 05:39:32 PM PDT 24 |
Jul 29 05:39:45 PM PDT 24 |
48624700 ps |
| T348 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.3884110848 |
|
|
Jul 29 05:39:46 PM PDT 24 |
Jul 29 05:40:00 PM PDT 24 |
24600300 ps |
| T116 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.932039711 |
|
|
Jul 29 05:39:05 PM PDT 24 |
Jul 29 05:39:23 PM PDT 24 |
294026000 ps |
| T224 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.856516794 |
|
|
Jul 29 05:39:34 PM PDT 24 |
Jul 29 05:39:51 PM PDT 24 |
100816500 ps |
| T1134 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.713976315 |
|
|
Jul 29 05:39:04 PM PDT 24 |
Jul 29 05:39:19 PM PDT 24 |
53817700 ps |
| T349 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2658432464 |
|
|
Jul 29 05:39:47 PM PDT 24 |
Jul 29 05:40:01 PM PDT 24 |
82549200 ps |
| T246 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3340953045 |
|
|
Jul 29 05:39:42 PM PDT 24 |
Jul 29 05:39:57 PM PDT 24 |
26828500 ps |
| T350 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3050549038 |
|
|
Jul 29 05:39:49 PM PDT 24 |
Jul 29 05:40:03 PM PDT 24 |
16301000 ps |
| T257 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.296977540 |
|
|
Jul 29 05:39:15 PM PDT 24 |
Jul 29 05:39:30 PM PDT 24 |
52286400 ps |
| T258 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2699151532 |
|
|
Jul 29 05:39:37 PM PDT 24 |
Jul 29 05:39:54 PM PDT 24 |
74702800 ps |
| T351 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.286018913 |
|
|
Jul 29 05:39:26 PM PDT 24 |
Jul 29 05:39:40 PM PDT 24 |
28333700 ps |
| T225 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2943616208 |
|
|
Jul 29 05:39:24 PM PDT 24 |
Jul 29 05:52:01 PM PDT 24 |
6414480200 ps |
| T1135 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1715125316 |
|
|
Jul 29 05:39:18 PM PDT 24 |
Jul 29 05:39:34 PM PDT 24 |
11606600 ps |
| T259 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2195293850 |
|
|
Jul 29 05:39:32 PM PDT 24 |
Jul 29 05:39:48 PM PDT 24 |
40394200 ps |
| T260 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.688209489 |
|
|
Jul 29 05:38:47 PM PDT 24 |
Jul 29 05:39:04 PM PDT 24 |
143991100 ps |
| T247 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.810773490 |
|
|
Jul 29 05:39:06 PM PDT 24 |
Jul 29 05:39:24 PM PDT 24 |
44175100 ps |
| T261 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1899626706 |
|
|
Jul 29 05:39:03 PM PDT 24 |
Jul 29 05:39:36 PM PDT 24 |
236213900 ps |
| T262 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.281922306 |
|
|
Jul 29 05:39:33 PM PDT 24 |
Jul 29 05:39:50 PM PDT 24 |
177398600 ps |
| T354 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1408696858 |
|
|
Jul 29 05:39:42 PM PDT 24 |
Jul 29 05:39:55 PM PDT 24 |
27649800 ps |
| T248 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2001324616 |
|
|
Jul 29 05:39:18 PM PDT 24 |
Jul 29 05:46:57 PM PDT 24 |
215902700 ps |
| T380 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1173377328 |
|
|
Jul 29 05:39:42 PM PDT 24 |
Jul 29 05:39:55 PM PDT 24 |
105979500 ps |
| T319 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1114932811 |
|
|
Jul 29 05:38:41 PM PDT 24 |
Jul 29 05:39:52 PM PDT 24 |
2772063600 ps |
| T250 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2041700562 |
|
|
Jul 29 05:38:41 PM PDT 24 |
Jul 29 05:45:12 PM PDT 24 |
395458600 ps |
| T249 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3654950411 |
|
|
Jul 29 05:38:47 PM PDT 24 |
Jul 29 05:39:04 PM PDT 24 |
125403600 ps |
| T263 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2436040753 |
|
|
Jul 29 05:39:32 PM PDT 24 |
Jul 29 05:39:48 PM PDT 24 |
36347700 ps |
| T352 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1015680120 |
|
|
Jul 29 05:39:14 PM PDT 24 |
Jul 29 05:39:28 PM PDT 24 |
27419600 ps |
| T251 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.4016467716 |
|
|
Jul 29 05:38:44 PM PDT 24 |
Jul 29 05:39:01 PM PDT 24 |
78694100 ps |
| T264 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.4276255802 |
|
|
Jul 29 05:39:04 PM PDT 24 |
Jul 29 05:39:24 PM PDT 24 |
123435200 ps |
| T381 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.123838595 |
|
|
Jul 29 05:39:37 PM PDT 24 |
Jul 29 05:39:51 PM PDT 24 |
47726900 ps |
| T1136 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3000327307 |
|
|
Jul 29 05:38:54 PM PDT 24 |
Jul 29 05:39:08 PM PDT 24 |
28730800 ps |
| T1137 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.259395091 |
|
|
Jul 29 05:39:00 PM PDT 24 |
Jul 29 05:39:16 PM PDT 24 |
17655900 ps |
| T318 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2602669401 |
|
|
Jul 29 05:38:43 PM PDT 24 |
Jul 29 05:39:03 PM PDT 24 |
115227400 ps |
| T1138 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1282614789 |
|
|
Jul 29 05:39:16 PM PDT 24 |
Jul 29 05:39:32 PM PDT 24 |
19349400 ps |
| T1139 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2872746363 |
|
|
Jul 29 05:39:33 PM PDT 24 |
Jul 29 05:39:47 PM PDT 24 |
40867100 ps |
| T1140 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.364956248 |
|
|
Jul 29 05:39:49 PM PDT 24 |
Jul 29 05:40:03 PM PDT 24 |
32020400 ps |
| T252 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3844196249 |
|
|
Jul 29 05:38:52 PM PDT 24 |
Jul 29 05:39:06 PM PDT 24 |
31656000 ps |
| T320 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1247307736 |
|
|
Jul 29 05:39:40 PM PDT 24 |
Jul 29 05:39:54 PM PDT 24 |
260746700 ps |
| T1141 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2374922053 |
|
|
Jul 29 05:38:58 PM PDT 24 |
Jul 29 05:39:37 PM PDT 24 |
1527768500 ps |
| T353 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.409808394 |
|
|
Jul 29 05:39:47 PM PDT 24 |
Jul 29 05:40:01 PM PDT 24 |
15316900 ps |
| T281 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3555070443 |
|
|
Jul 29 05:39:07 PM PDT 24 |
Jul 29 05:53:58 PM PDT 24 |
2614692600 ps |
| T286 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3056865670 |
|
|
Jul 29 05:39:04 PM PDT 24 |
Jul 29 05:39:24 PM PDT 24 |
642107300 ps |
| T1142 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.3447969487 |
|
|
Jul 29 05:39:47 PM PDT 24 |
Jul 29 05:40:01 PM PDT 24 |
18466200 ps |
| T287 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2603191485 |
|
|
Jul 29 05:39:30 PM PDT 24 |
Jul 29 05:39:47 PM PDT 24 |
517470500 ps |
| T1143 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2702930973 |
|
|
Jul 29 05:39:20 PM PDT 24 |
Jul 29 05:39:33 PM PDT 24 |
16870300 ps |
| T1144 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2008989661 |
|
|
Jul 29 05:39:12 PM PDT 24 |
Jul 29 05:39:28 PM PDT 24 |
28226700 ps |
| T1145 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2120840423 |
|
|
Jul 29 05:38:39 PM PDT 24 |
Jul 29 05:38:56 PM PDT 24 |
103344300 ps |
| T1146 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3463482899 |
|
|
Jul 29 05:38:43 PM PDT 24 |
Jul 29 05:38:57 PM PDT 24 |
18829500 ps |
| T1147 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.214407148 |
|
|
Jul 29 05:39:29 PM PDT 24 |
Jul 29 05:39:45 PM PDT 24 |
27264100 ps |
| T1148 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.130832939 |
|
|
Jul 29 05:38:54 PM PDT 24 |
Jul 29 05:39:27 PM PDT 24 |
487933200 ps |
| T1149 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3555367898 |
|
|
Jul 29 05:39:45 PM PDT 24 |
Jul 29 05:39:59 PM PDT 24 |
19491600 ps |
| T1150 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2573519327 |
|
|
Jul 29 05:39:15 PM PDT 24 |
Jul 29 05:39:33 PM PDT 24 |
53885300 ps |
| T321 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2655693758 |
|
|
Jul 29 05:38:59 PM PDT 24 |
Jul 29 05:39:17 PM PDT 24 |
264120500 ps |
| T1151 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3357457664 |
|
|
Jul 29 05:39:13 PM PDT 24 |
Jul 29 05:39:29 PM PDT 24 |
89624300 ps |
| T1152 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2866957982 |
|
|
Jul 29 05:38:58 PM PDT 24 |
Jul 29 05:39:17 PM PDT 24 |
253203300 ps |
| T1153 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.4087314212 |
|
|
Jul 29 05:39:37 PM PDT 24 |
Jul 29 05:39:50 PM PDT 24 |
24765300 ps |
| T1154 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.4076234631 |
|
|
Jul 29 05:38:58 PM PDT 24 |
Jul 29 05:39:14 PM PDT 24 |
40909300 ps |
| T253 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.801550666 |
|
|
Jul 29 05:38:57 PM PDT 24 |
Jul 29 05:39:11 PM PDT 24 |
47682400 ps |
| T275 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1707519995 |
|
|
Jul 29 05:39:22 PM PDT 24 |
Jul 29 05:39:39 PM PDT 24 |
82035400 ps |
| T1155 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1437592022 |
|
|
Jul 29 05:39:05 PM PDT 24 |
Jul 29 05:39:22 PM PDT 24 |
29090600 ps |
| T1156 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2740632477 |
|
|
Jul 29 05:38:53 PM PDT 24 |
Jul 29 05:39:07 PM PDT 24 |
14593600 ps |
| T270 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1346983655 |
|
|
Jul 29 05:39:14 PM PDT 24 |
Jul 29 05:39:33 PM PDT 24 |
66909200 ps |
| T1157 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1220497543 |
|
|
Jul 29 05:38:37 PM PDT 24 |
Jul 29 05:39:08 PM PDT 24 |
36483800 ps |
| T1158 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.926075707 |
|
|
Jul 29 05:39:37 PM PDT 24 |
Jul 29 05:39:55 PM PDT 24 |
238702400 ps |
| T1159 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2453042946 |
|
|
Jul 29 05:39:14 PM PDT 24 |
Jul 29 05:39:31 PM PDT 24 |
56758700 ps |
| T1160 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2980649603 |
|
|
Jul 29 05:39:07 PM PDT 24 |
Jul 29 05:39:22 PM PDT 24 |
21368300 ps |
| T279 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2503405356 |
|
|
Jul 29 05:39:38 PM PDT 24 |
Jul 29 05:39:59 PM PDT 24 |
47584700 ps |
| T1161 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1202922615 |
|
|
Jul 29 05:39:33 PM PDT 24 |
Jul 29 05:39:47 PM PDT 24 |
25002000 ps |
| T1162 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2961436047 |
|
|
Jul 29 05:39:47 PM PDT 24 |
Jul 29 05:40:01 PM PDT 24 |
17876100 ps |
| T254 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1414181032 |
|
|
Jul 29 05:38:42 PM PDT 24 |
Jul 29 05:38:55 PM PDT 24 |
27559500 ps |
| T322 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1850816216 |
|
|
Jul 29 05:38:52 PM PDT 24 |
Jul 29 05:39:08 PM PDT 24 |
62208200 ps |
| T1163 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3945119334 |
|
|
Jul 29 05:38:45 PM PDT 24 |
Jul 29 05:39:23 PM PDT 24 |
324391500 ps |
| T288 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1330390525 |
|
|
Jul 29 05:39:30 PM PDT 24 |
Jul 29 05:52:12 PM PDT 24 |
1356278000 ps |
| T1164 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3896618010 |
|
|
Jul 29 05:39:30 PM PDT 24 |
Jul 29 05:39:44 PM PDT 24 |
11464100 ps |
| T1165 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3606112576 |
|
|
Jul 29 05:39:20 PM PDT 24 |
Jul 29 05:39:33 PM PDT 24 |
26392100 ps |
| T1166 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2227020711 |
|
|
Jul 29 05:39:17 PM PDT 24 |
Jul 29 05:39:30 PM PDT 24 |
17157000 ps |
| T284 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.437136973 |
|
|
Jul 29 05:39:31 PM PDT 24 |
Jul 29 05:47:14 PM PDT 24 |
1522840400 ps |
| T1167 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.3110300137 |
|
|
Jul 29 05:39:42 PM PDT 24 |
Jul 29 05:39:56 PM PDT 24 |
48181000 ps |
| T1168 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.4109084463 |
|
|
Jul 29 05:39:39 PM PDT 24 |
Jul 29 05:39:52 PM PDT 24 |
19124500 ps |
| T1169 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.1401712042 |
|
|
Jul 29 05:38:51 PM PDT 24 |
Jul 29 05:39:05 PM PDT 24 |
49984800 ps |
| T283 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2434236133 |
|
|
Jul 29 05:39:30 PM PDT 24 |
Jul 29 05:39:48 PM PDT 24 |
27817100 ps |
| T271 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3452534772 |
|
|
Jul 29 05:39:06 PM PDT 24 |
Jul 29 05:39:25 PM PDT 24 |
159156200 ps |
| T1170 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3161766961 |
|
|
Jul 29 05:39:12 PM PDT 24 |
Jul 29 05:39:27 PM PDT 24 |
28049100 ps |
| T1171 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.4288581530 |
|
|
Jul 29 05:38:57 PM PDT 24 |
Jul 29 05:39:13 PM PDT 24 |
22756300 ps |
| T1172 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.515466836 |
|
|
Jul 29 05:38:43 PM PDT 24 |
Jul 29 05:38:59 PM PDT 24 |
32180300 ps |
| T1173 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.1605666933 |
|
|
Jul 29 05:39:47 PM PDT 24 |
Jul 29 05:40:01 PM PDT 24 |
26020000 ps |
| T1174 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3583973955 |
|
|
Jul 29 05:39:22 PM PDT 24 |
Jul 29 05:39:39 PM PDT 24 |
39681900 ps |
| T1175 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2521990226 |
|
|
Jul 29 05:39:12 PM PDT 24 |
Jul 29 05:39:25 PM PDT 24 |
43032100 ps |
| T1176 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.4226614596 |
|
|
Jul 29 05:39:17 PM PDT 24 |
Jul 29 05:39:31 PM PDT 24 |
22832800 ps |
| T383 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3387421733 |
|
|
Jul 29 05:39:38 PM PDT 24 |
Jul 29 05:46:01 PM PDT 24 |
188172400 ps |
| T1177 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3214464677 |
|
|
Jul 29 05:38:46 PM PDT 24 |
Jul 29 05:39:04 PM PDT 24 |
712125900 ps |
| T323 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.514084489 |
|
|
Jul 29 05:38:58 PM PDT 24 |
Jul 29 05:39:16 PM PDT 24 |
116157500 ps |
| T1178 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3956850360 |
|
|
Jul 29 05:39:23 PM PDT 24 |
Jul 29 05:39:38 PM PDT 24 |
39142500 ps |
| T1179 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2514414638 |
|
|
Jul 29 05:39:44 PM PDT 24 |
Jul 29 05:39:57 PM PDT 24 |
30609900 ps |
| T1180 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2543986279 |
|
|
Jul 29 05:38:45 PM PDT 24 |
Jul 29 05:38:59 PM PDT 24 |
52282400 ps |
| T1181 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.4181482588 |
|
|
Jul 29 05:39:45 PM PDT 24 |
Jul 29 05:39:58 PM PDT 24 |
43505900 ps |
| T1182 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2397579547 |
|
|
Jul 29 05:39:39 PM PDT 24 |
Jul 29 05:39:56 PM PDT 24 |
87433600 ps |
| T1183 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1707377588 |
|
|
Jul 29 05:39:16 PM PDT 24 |
Jul 29 05:39:50 PM PDT 24 |
262113000 ps |
| T1184 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.4221561141 |
|
|
Jul 29 05:38:39 PM PDT 24 |
Jul 29 05:38:53 PM PDT 24 |
25300700 ps |
| T1185 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2685959791 |
|
|
Jul 29 05:39:11 PM PDT 24 |
Jul 29 05:39:26 PM PDT 24 |
34564800 ps |
| T1186 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.778351410 |
|
|
Jul 29 05:39:44 PM PDT 24 |
Jul 29 05:39:58 PM PDT 24 |
49918500 ps |
| T1187 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3521299992 |
|
|
Jul 29 05:39:27 PM PDT 24 |
Jul 29 05:39:44 PM PDT 24 |
37641700 ps |
| T1188 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1993817975 |
|
|
Jul 29 05:39:15 PM PDT 24 |
Jul 29 05:39:32 PM PDT 24 |
204421600 ps |
| T278 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2085276006 |
|
|
Jul 29 05:39:01 PM PDT 24 |
Jul 29 05:39:20 PM PDT 24 |
186499700 ps |
| T1189 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3898444366 |
|
|
Jul 29 05:39:46 PM PDT 24 |
Jul 29 05:40:00 PM PDT 24 |
26285300 ps |
| T1190 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2390147410 |
|
|
Jul 29 05:38:47 PM PDT 24 |
Jul 29 05:39:26 PM PDT 24 |
45104100 ps |
| T1191 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1835235620 |
|
|
Jul 29 05:39:32 PM PDT 24 |
Jul 29 05:39:49 PM PDT 24 |
18403900 ps |
| T1192 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.784734813 |
|
|
Jul 29 05:39:05 PM PDT 24 |
Jul 29 05:39:22 PM PDT 24 |
21072800 ps |
| T276 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.833495323 |
|
|
Jul 29 05:39:39 PM PDT 24 |
Jul 29 05:39:58 PM PDT 24 |
467287100 ps |
| T1193 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2936935798 |
|
|
Jul 29 05:39:36 PM PDT 24 |
Jul 29 05:39:49 PM PDT 24 |
20282900 ps |
| T324 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1572870036 |
|
|
Jul 29 05:38:48 PM PDT 24 |
Jul 29 05:39:19 PM PDT 24 |
403429300 ps |
| T325 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.4261590417 |
|
|
Jul 29 05:39:27 PM PDT 24 |
Jul 29 05:39:43 PM PDT 24 |
110974600 ps |
| T1194 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3505759710 |
|
|
Jul 29 05:38:43 PM PDT 24 |
Jul 29 05:38:57 PM PDT 24 |
17007300 ps |
| T1195 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1047861131 |
|
|
Jul 29 05:38:42 PM PDT 24 |
Jul 29 05:38:55 PM PDT 24 |
52476100 ps |
| T384 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2910328394 |
|
|
Jul 29 05:39:03 PM PDT 24 |
Jul 29 05:45:25 PM PDT 24 |
770273000 ps |
| T1196 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.3863121763 |
|
|
Jul 29 05:38:58 PM PDT 24 |
Jul 29 05:39:11 PM PDT 24 |
198801600 ps |
| T1197 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.585454438 |
|
|
Jul 29 05:39:15 PM PDT 24 |
Jul 29 05:39:34 PM PDT 24 |
157207900 ps |
| T277 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1034442940 |
|
|
Jul 29 05:39:01 PM PDT 24 |
Jul 29 05:53:56 PM PDT 24 |
5551347100 ps |
| T1198 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.286215120 |
|
|
Jul 29 05:39:32 PM PDT 24 |
Jul 29 05:39:46 PM PDT 24 |
14473500 ps |
| T326 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2489202135 |
|
|
Jul 29 05:38:59 PM PDT 24 |
Jul 29 05:39:51 PM PDT 24 |
12234124800 ps |
| T1199 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.4271731504 |
|
|
Jul 29 05:39:20 PM PDT 24 |
Jul 29 05:39:37 PM PDT 24 |
90112600 ps |
| T1200 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.469890768 |
|
|
Jul 29 05:39:04 PM PDT 24 |
Jul 29 05:39:18 PM PDT 24 |
152748400 ps |
| T1201 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2437719825 |
|
|
Jul 29 05:39:19 PM PDT 24 |
Jul 29 05:39:48 PM PDT 24 |
94838800 ps |
| T327 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2600875335 |
|
|
Jul 29 05:38:42 PM PDT 24 |
Jul 29 05:46:22 PM PDT 24 |
860083200 ps |
| T328 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3477805788 |
|
|
Jul 29 05:39:14 PM PDT 24 |
Jul 29 05:39:31 PM PDT 24 |
218196400 ps |
| T1202 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3446558964 |
|
|
Jul 29 05:38:51 PM PDT 24 |
Jul 29 05:39:07 PM PDT 24 |
42845600 ps |
| T1203 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1466188331 |
|
|
Jul 29 05:38:43 PM PDT 24 |
Jul 29 05:39:09 PM PDT 24 |
34550500 ps |
| T1204 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.325452778 |
|
|
Jul 29 05:39:03 PM PDT 24 |
Jul 29 05:39:19 PM PDT 24 |
13549600 ps |
| T285 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3637066508 |
|
|
Jul 29 05:39:27 PM PDT 24 |
Jul 29 05:39:46 PM PDT 24 |
597831200 ps |
| T272 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1400656126 |
|
|
Jul 29 05:39:19 PM PDT 24 |
Jul 29 05:39:39 PM PDT 24 |
102992800 ps |
| T1205 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.4049315475 |
|
|
Jul 29 05:38:54 PM PDT 24 |
Jul 29 05:39:55 PM PDT 24 |
2434631900 ps |
| T1206 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.650428608 |
|
|
Jul 29 05:38:52 PM PDT 24 |
Jul 29 05:39:10 PM PDT 24 |
114174500 ps |
| T1207 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.242650703 |
|
|
Jul 29 05:38:46 PM PDT 24 |
Jul 29 05:39:58 PM PDT 24 |
10402874200 ps |
| T388 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2721997037 |
|
|
Jul 29 05:39:19 PM PDT 24 |
Jul 29 05:46:50 PM PDT 24 |
3317449100 ps |
| T1208 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2851138204 |
|
|
Jul 29 05:38:43 PM PDT 24 |
Jul 29 05:38:57 PM PDT 24 |
35686400 ps |
| T1209 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3509570247 |
|
|
Jul 29 05:39:43 PM PDT 24 |
Jul 29 05:39:56 PM PDT 24 |
15563000 ps |
| T1210 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1245550010 |
|
|
Jul 29 05:39:00 PM PDT 24 |
Jul 29 05:39:16 PM PDT 24 |
13486600 ps |
| T1211 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.400242853 |
|
|
Jul 29 05:38:54 PM PDT 24 |
Jul 29 05:39:11 PM PDT 24 |
103832700 ps |
| T1212 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3322894684 |
|
|
Jul 29 05:39:28 PM PDT 24 |
Jul 29 05:39:44 PM PDT 24 |
36839600 ps |
| T1213 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1548435338 |
|
|
Jul 29 05:39:12 PM PDT 24 |
Jul 29 05:39:43 PM PDT 24 |
774481800 ps |
| T1214 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2325842957 |
|
|
Jul 29 05:39:28 PM PDT 24 |
Jul 29 05:39:43 PM PDT 24 |
44113600 ps |
| T391 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.710030191 |
|
|
Jul 29 05:39:30 PM PDT 24 |
Jul 29 05:47:02 PM PDT 24 |
337866000 ps |
| T1215 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1424128380 |
|
|
Jul 29 05:39:44 PM PDT 24 |
Jul 29 05:39:58 PM PDT 24 |
16240700 ps |
| T1216 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.511329797 |
|
|
Jul 29 05:38:46 PM PDT 24 |
Jul 29 05:39:02 PM PDT 24 |
61803100 ps |
| T1217 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1327652146 |
|
|
Jul 29 05:39:12 PM PDT 24 |
Jul 29 05:39:26 PM PDT 24 |
31328800 ps |
| T1218 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1323255484 |
|
|
Jul 29 05:39:43 PM PDT 24 |
Jul 29 05:39:56 PM PDT 24 |
18134800 ps |
| T1219 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1554038584 |
|
|
Jul 29 05:39:14 PM PDT 24 |
Jul 29 05:39:28 PM PDT 24 |
14481300 ps |
| T1220 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.242857207 |
|
|
Jul 29 05:39:37 PM PDT 24 |
Jul 29 05:39:53 PM PDT 24 |
108169200 ps |
| T385 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1238787334 |
|
|
Jul 29 05:39:12 PM PDT 24 |
Jul 29 05:54:42 PM PDT 24 |
1331177900 ps |
| T1221 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2012921882 |
|
|
Jul 29 05:39:44 PM PDT 24 |
Jul 29 05:39:58 PM PDT 24 |
244259400 ps |
| T386 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.201257570 |
|
|
Jul 29 05:39:14 PM PDT 24 |
Jul 29 05:46:40 PM PDT 24 |
182780200 ps |
| T1222 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2648847866 |
|
|
Jul 29 05:39:33 PM PDT 24 |
Jul 29 05:39:49 PM PDT 24 |
25309800 ps |
| T1223 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2305677046 |
|
|
Jul 29 05:39:19 PM PDT 24 |
Jul 29 05:39:36 PM PDT 24 |
98495900 ps |
| T1224 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.3868218797 |
|
|
Jul 29 05:39:42 PM PDT 24 |
Jul 29 05:39:55 PM PDT 24 |
57327400 ps |
| T1225 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3110366135 |
|
|
Jul 29 05:39:11 PM PDT 24 |
Jul 29 05:39:27 PM PDT 24 |
45160300 ps |
| T1226 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1416583154 |
|
|
Jul 29 05:38:41 PM PDT 24 |
Jul 29 05:38:58 PM PDT 24 |
649802100 ps |
| T1227 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1264287085 |
|
|
Jul 29 05:39:02 PM PDT 24 |
Jul 29 05:39:18 PM PDT 24 |
31178300 ps |
| T1228 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.460674726 |
|
|
Jul 29 05:39:42 PM PDT 24 |
Jul 29 05:39:56 PM PDT 24 |
27812400 ps |
| T1229 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2828246943 |
|
|
Jul 29 05:38:39 PM PDT 24 |
Jul 29 05:38:55 PM PDT 24 |
50287400 ps |
| T1230 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.308725651 |
|
|
Jul 29 05:39:03 PM PDT 24 |
Jul 29 05:39:19 PM PDT 24 |
336447000 ps |
| T1231 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1394685891 |
|
|
Jul 29 05:38:48 PM PDT 24 |
Jul 29 05:39:09 PM PDT 24 |
343074000 ps |
| T1232 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1952153416 |
|
|
Jul 29 05:39:12 PM PDT 24 |
Jul 29 05:39:26 PM PDT 24 |
28037600 ps |
| T1233 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1342216699 |
|
|
Jul 29 05:38:39 PM PDT 24 |
Jul 29 05:39:38 PM PDT 24 |
1293086100 ps |
| T1234 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1715451050 |
|
|
Jul 29 05:39:00 PM PDT 24 |
Jul 29 05:39:14 PM PDT 24 |
85514300 ps |
| T1235 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1562039733 |
|
|
Jul 29 05:38:58 PM PDT 24 |
Jul 29 05:39:36 PM PDT 24 |
69742800 ps |
| T1236 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2692097811 |
|
|
Jul 29 05:39:16 PM PDT 24 |
Jul 29 05:39:34 PM PDT 24 |
263751100 ps |
| T1237 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1004441462 |
|
|
Jul 29 05:39:24 PM PDT 24 |
Jul 29 05:39:59 PM PDT 24 |
1138106200 ps |
| T1238 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2385519794 |
|
|
Jul 29 05:38:47 PM PDT 24 |
Jul 29 05:39:04 PM PDT 24 |
23652400 ps |
| T1239 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2869183904 |
|
|
Jul 29 05:38:48 PM PDT 24 |
Jul 29 05:39:27 PM PDT 24 |
3131038300 ps |
| T1240 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.773107299 |
|
|
Jul 29 05:39:39 PM PDT 24 |
Jul 29 05:39:54 PM PDT 24 |
33919200 ps |
| T390 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3405881444 |
|
|
Jul 29 05:39:15 PM PDT 24 |
Jul 29 05:54:12 PM PDT 24 |
672616800 ps |
| T282 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3416819572 |
|
|
Jul 29 05:39:37 PM PDT 24 |
Jul 29 05:39:57 PM PDT 24 |
65398400 ps |
| T255 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.4089716589 |
|
|
Jul 29 05:38:48 PM PDT 24 |
Jul 29 05:39:02 PM PDT 24 |
18450200 ps |
| T1241 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1006021451 |
|
|
Jul 29 05:39:42 PM PDT 24 |
Jul 29 05:39:56 PM PDT 24 |
19474700 ps |
| T1242 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3155590683 |
|
|
Jul 29 05:39:44 PM PDT 24 |
Jul 29 05:39:58 PM PDT 24 |
153740900 ps |
| T1243 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1229038742 |
|
|
Jul 29 05:39:01 PM PDT 24 |
Jul 29 05:39:15 PM PDT 24 |
29922900 ps |
| T1244 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2889150071 |
|
|
Jul 29 05:39:23 PM PDT 24 |
Jul 29 05:39:41 PM PDT 24 |
38338900 ps |
| T387 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.570625408 |
|
|
Jul 29 05:38:46 PM PDT 24 |
Jul 29 05:53:52 PM PDT 24 |
810972700 ps |
| T389 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3923819943 |
|
|
Jul 29 05:38:46 PM PDT 24 |
Jul 29 05:51:29 PM PDT 24 |
1505365300 ps |
| T1245 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1719706744 |
|
|
Jul 29 05:39:16 PM PDT 24 |
Jul 29 05:39:33 PM PDT 24 |
409794200 ps |
| T1246 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.468911137 |
|
|
Jul 29 05:39:12 PM PDT 24 |
Jul 29 05:39:28 PM PDT 24 |
12206100 ps |
| T1247 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.875664732 |
|
|
Jul 29 05:39:38 PM PDT 24 |
Jul 29 05:39:52 PM PDT 24 |
110125900 ps |
| T289 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1018766413 |
|
|
Jul 29 05:39:18 PM PDT 24 |
Jul 29 05:39:34 PM PDT 24 |
35935000 ps |
| T1248 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1212888899 |
|
|
Jul 29 05:39:06 PM PDT 24 |
Jul 29 05:39:20 PM PDT 24 |
52732600 ps |
| T1249 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2610280151 |
|
|
Jul 29 05:39:23 PM PDT 24 |
Jul 29 05:39:36 PM PDT 24 |
58185200 ps |
| T1250 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1560417117 |
|
|
Jul 29 05:39:43 PM PDT 24 |
Jul 29 05:39:58 PM PDT 24 |
85666300 ps |
| T1251 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.646203547 |
|
|
Jul 29 05:39:43 PM PDT 24 |
Jul 29 05:39:57 PM PDT 24 |
52848600 ps |
| T1252 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1342489540 |
|
|
Jul 29 05:39:25 PM PDT 24 |
Jul 29 05:39:45 PM PDT 24 |
80188300 ps |
| T392 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.4225664399 |
|
|
Jul 29 05:39:36 PM PDT 24 |
Jul 29 05:52:09 PM PDT 24 |
673203600 ps |
| T280 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2411448543 |
|
|
Jul 29 05:39:12 PM PDT 24 |
Jul 29 05:39:30 PM PDT 24 |
76073600 ps |