Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	289570	1		T1	2		T2	1		T3	2
all_values[1]	289570	1		T1	2		T2	1		T3	2
all_values[2]	289570	1		T1	2		T2	1		T3	2
all_values[3]	289570	1		T1	2		T2	1		T3	2
all_values[4]	289570	1		T1	2		T2	1		T3	2
all_values[5]	289570	1		T1	2		T2	1		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	585620	1		T1	12		T2	6		T3	12
auto[1]	1151800	1		T27	11328		T5	14208		T22	12520

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	844932	1		T1	7		T2	4		T3	7
auto[1]	892488	1		T1	5		T2	2		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	289427	1		T1	2		T2	1		T3	2
all_values[0]	auto[1]	auto[1]	143	1		T252	3		T253	1		T347	3
all_values[1]	auto[0]	auto[1]	289420	1		T1	2		T2	1		T3	2
all_values[1]	auto[1]	auto[1]	150	1		T252	5		T253	4		T347	4
all_values[2]	auto[0]	auto[0]	1655	1		T1	2		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	62	1		T252	2		T253	2		T347	2
all_values[2]	auto[1]	auto[0]	287802	1		T27	2832		T5	3552		T22	3130
all_values[2]	auto[1]	auto[1]	51	1		T252	3		T347	1		T348	2
all_values[3]	auto[0]	auto[0]	1623	1		T1	2		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	58	1		T252	2		T253	1		T348	1
all_values[3]	auto[1]	auto[0]	83759	1		T27	1416		T5	1776		T22	1565
all_values[3]	auto[1]	auto[1]	204130	1		T27	1416		T5	1776		T22	1565
all_values[4]	auto[0]	auto[0]	1159	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	533	1		T1	1		T3	1		T4	1
all_values[4]	auto[1]	auto[0]	179513	1		T27	1416		T5	1776		T22	1565
all_values[4]	auto[1]	auto[1]	108365	1		T27	1416		T5	1776		T22	1565
all_values[5]	auto[0]	auto[0]	1601	1		T1	2		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	82	1		T39	1		T40	1		T41	1
all_values[5]	auto[1]	auto[0]	287820	1		T27	2832		T5	3552		T22	3130
all_values[5]	auto[1]	auto[1]	67	1		T252	5		T347	1		T348	1