Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	243472	1		T1	9		T2	942		T3	402
auto[FlashEraseBank]	266068	1		T1	8		T18	2		T4	6

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	258797	1		T1	7		T2	490		T3	12
auto[FlashOpProgram]	230522	1		T1	5		T2	226		T3	384
auto[FlashOpErase]	16221	1		T1	5		T2	226		T3	6
auto[FlashOpInvalid]	4000	1		T47	200		T149	200		T270	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	258797	1		T1	7		T2	490		T3	12
op[FlashOpProgram]	230522	1		T1	5		T2	226		T3	384
op[FlashOpErase]	16221	1		T1	5		T2	226		T3	6
read_erase_read	538	1		T1	1		T3	2		T50	14
read_prog_read	826	1		T1	1		T18	1		T4	9

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	367866	1		T1	17		T18	3		T4	20
auto[FlashPartInfo]	138360	1		T2	942		T3	402		T18	9
auto[FlashPartInfo1]	690	1		T45	1		T59	3		T145	6
auto[FlashPartInfo2]	2624	1		T18	1		T29	2		T67	6

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	189185	1		T1	7		T18	2		T4	10
auto[FlashPartData]	auto[FlashOpProgram]	171136	1		T1	5		T18	1		T4	10
auto[FlashPartData]	auto[FlashOpErase]	3617	1		T1	5		T50	6		T145	1
auto[FlashPartData]	auto[FlashOpInvalid]	3928	1		T47	200		T149	194		T270	200
auto[FlashPartInfo]	auto[FlashOpRead]	67454	1		T2	490		T3	12		T18	9
auto[FlashPartInfo]	auto[FlashOpProgram]	58257	1		T2	226		T3	384		T28	1
auto[FlashPartInfo]	auto[FlashOpErase]	12581	1		T2	226		T3	6		T50	8
auto[FlashPartInfo]	auto[FlashOpInvalid]	68	1		T149	4		T432	2		T433	4
auto[FlashPartInfo1]	auto[FlashOpRead]	523	1		T45	1		T59	3		T145	6
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T151	32		T77	1		T131	32
auto[FlashPartInfo1]	auto[FlashOpErase]	2	1		T155	1		T434	1		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T434	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1635	1		T18	1		T29	2		T64	1
auto[FlashPartInfo2]	auto[FlashOpProgram]	966	1		T67	6		T68	5		T45	1
auto[FlashPartInfo2]	auto[FlashOpErase]	21	1		T50	1		T149	1		T152	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	2	1		T149	2		-	-		-	-