Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	1	31	96.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	1	31	96.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31924	1		T1	17		T2	444		T4	40
auto[1]	56	1		T50	5		T39	3		T214	1
auto[2]	50	1		T37	5		T78	4		T170	4
auto[3]	230	1		T28	1		T29	1		T37	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8075	1		T1	5		T2	111		T4	10
evic_idx[1]	8067	1		T1	4		T2	111		T4	10
evic_idx[2]	8053	1		T1	4		T2	111		T4	10
evic_idx[3]	8065	1		T1	4		T2	111		T4	10

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	31301	1		T2	444		T50	14		T49	660
evic_op[2]	355	1		T1	1		T4	40		T28	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	1	31	96.88	1

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[2]]	[evic_op[2]]	[auto[2]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7764	1		T2	111		T49	165		T47	100
evic_idx[0]	evic_op[1]	auto[1]	16	1		T50	1		T364	3		T365	3
evic_idx[0]	evic_op[1]	auto[2]	3	1		T366	1		T367	2		-	-
evic_idx[0]	evic_op[1]	auto[3]	48	1		T50	2		T368	3		T369	3
evic_idx[0]	evic_op[2]	auto[0]	73	1		T1	1		T4	10		T77	1
evic_idx[0]	evic_op[2]	auto[1]	3	1		T39	1		T370	1		T371	1
evic_idx[0]	evic_op[2]	auto[2]	4	1		T37	1		T372	1		T373	1
evic_idx[0]	evic_op[2]	auto[3]	13	1		T38	1		T374	1		T372	1
evic_idx[1]	evic_op[1]	auto[0]	7764	1		T2	111		T49	165		T47	100
evic_idx[1]	evic_op[1]	auto[1]	11	1		T50	2		T364	2		T365	1
evic_idx[1]	evic_op[1]	auto[2]	4	1		T366	2		T367	2		-	-
evic_idx[1]	evic_op[1]	auto[3]	48	1		T50	1		T368	4		T369	3
evic_idx[1]	evic_op[2]	auto[0]	70	1		T4	10		T77	1		T375	2
evic_idx[1]	evic_op[2]	auto[1]	3	1		T39	1		T376	1		T377	1
evic_idx[1]	evic_op[2]	auto[2]	5	1		T37	2		T378	1		T379	2
evic_idx[1]	evic_op[2]	auto[3]	11	1		T28	1		T29	1		T60	1
evic_idx[2]	evic_op[1]	auto[0]	7763	1		T2	111		T49	165		T47	100
evic_idx[2]	evic_op[1]	auto[1]	8	1		T50	1		T364	1		T365	1
evic_idx[2]	evic_op[1]	auto[2]	4	1		T365	1		T366	1		T367	2
evic_idx[2]	evic_op[1]	auto[3]	43	1		T50	3		T368	2		T369	4
evic_idx[2]	evic_op[2]	auto[0]	71	1		T4	10		T77	1		T375	2
evic_idx[2]	evic_op[2]	auto[1]	4	1		T277	1		T380	1		T378	1
evic_idx[2]	evic_op[2]	auto[3]	9	1		T42	1		T122	1		T381	1
evic_idx[3]	evic_op[1]	auto[0]	7764	1		T2	111		T49	165		T47	100
evic_idx[3]	evic_op[1]	auto[1]	9	1		T50	1		T364	2		T365	2
evic_idx[3]	evic_op[1]	auto[2]	4	1		T365	1		T366	1		T367	2
evic_idx[3]	evic_op[1]	auto[3]	48	1		T50	3		T368	4		T369	3
evic_idx[3]	evic_op[2]	auto[0]	71	1		T4	10		T77	1		T375	2
evic_idx[3]	evic_op[2]	auto[1]	2	1		T39	1		T214	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	6	1		T37	2		T373	1		T379	1
evic_idx[3]	evic_op[2]	auto[3]	10	1		T37	1		T382	1		T383	1