Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	8232	1		T341	971		T353	882		T354	1998
rd_lvl[2]	10472	1		T355	2311		T341	261		T356	1241
rd_lvl[3]	18402	1		T355	2162		T357	1064		T356	1876
rd_lvl[4]	29278	1		T355	1003		T357	1366		T356	297
rd_lvl[5]	23333	1		T238	915		T355	1798		T357	132
rd_lvl[6]	23747	1		T235	366		T238	2703		T329	1098
rd_lvl[7]	15595	1		T71	500		T72	591		T235	211
rd_lvl[8]	22052	1		T71	239		T72	228		T235	50
rd_lvl[9]	10050	1		T71	151		T72	129		T235	211
rd_lvl[10]	11996	1		T71	122		T72	126		T235	211
rd_lvl[11]	4623	1		T22	514		T330	16		T358	212
rd_lvl[12]	3736	1		T22	1051		T359	360		T354	1
rd_lvl[13]	641	1		T36	247		T359	192		T357	43
rd_lvl[14]	4914	1		T27	1416		T5	1404		T36	1568
rd_lvl[15]	3361	1		T5	372		T35	240		T359	10