Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	289570	1		T1	2		T2	1		T3	2
all_pins[1]	289570	1		T1	2		T2	1		T3	2
all_pins[2]	289570	1		T1	2		T2	1		T3	2
all_pins[3]	289570	1		T1	2		T2	1		T3	2
all_pins[4]	289570	1		T1	2		T2	1		T3	2
all_pins[5]	289570	1		T1	2		T2	1		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1413420	1		T1	12		T2	6		T3	12
values[0x1]	324000	1		T27	2832		T5	3552		T22	3130
transitions[0x0=>0x1]	280589	1		T27	2832		T5	3552		T22	3130
transitions[0x1=>0x0]	280580	1		T27	2832		T5	3552		T22	3130

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	289427	1		T1	2		T2	1		T3	2
all_pins[0]	values[0x1]	143	1		T252	3		T253	1		T347	3
all_pins[0]	transitions[0x0=>0x1]	78	1		T252	2		T253	1		T348	1
all_pins[0]	transitions[0x1=>0x0]	85	1		T252	4		T253	4		T347	1
all_pins[1]	values[0x0]	289420	1		T1	2		T2	1		T3	2
all_pins[1]	values[0x1]	150	1		T252	5		T253	4		T347	4
all_pins[1]	transitions[0x0=>0x1]	125	1		T252	4		T253	4		T347	3
all_pins[1]	transitions[0x1=>0x0]	5829	1		T35	266		T384	275		T385	137
all_pins[2]	values[0x0]	283716	1		T1	2		T2	1		T3	2
all_pins[2]	values[0x1]	5854	1		T35	266		T384	275		T385	137
all_pins[2]	transitions[0x0=>0x1]	36	1		T252	2		T348	1		T349	2
all_pins[2]	transitions[0x1=>0x0]	190513	1		T27	1416		T5	1776		T22	1565
all_pins[3]	values[0x0]	93239	1		T1	2		T2	1		T3	2
all_pins[3]	values[0x1]	196331	1		T27	1416		T5	1776		T22	1565
all_pins[3]	transitions[0x0=>0x1]	158887	1		T27	1416		T5	1776		T22	1565
all_pins[3]	transitions[0x1=>0x0]	84011	1		T27	1416		T5	1776		T22	1565
all_pins[4]	values[0x0]	168115	1		T1	2		T2	1		T3	2
all_pins[4]	values[0x1]	121455	1		T27	1416		T5	1776		T22	1565
all_pins[4]	transitions[0x0=>0x1]	121432	1		T27	1416		T5	1776		T22	1565
all_pins[4]	transitions[0x1=>0x0]	44	1		T252	2		T347	1		T348	1
all_pins[5]	values[0x0]	289503	1		T1	2		T2	1		T3	2
all_pins[5]	values[0x1]	67	1		T252	5		T347	1		T348	1
all_pins[5]	transitions[0x0=>0x1]	31	1		T252	2		T347	1		T348	1
all_pins[5]	transitions[0x1=>0x0]	98	1		T252	1		T253	1		T347	2