| T1077 |
/workspace/coverage/default/3.flash_ctrl_hw_sec_otp.417096751 |
|
|
Jul 30 05:00:07 PM PDT 24 |
Jul 30 05:02:37 PM PDT 24 |
22523428000 ps |
| T1078 |
/workspace/coverage/default/1.flash_ctrl_mp_regions.1585875905 |
|
|
Jul 30 04:59:17 PM PDT 24 |
Jul 30 05:10:55 PM PDT 24 |
25845278400 ps |
| T1079 |
/workspace/coverage/default/49.flash_ctrl_alert_test.4242325934 |
|
|
Jul 30 05:09:23 PM PDT 24 |
Jul 30 05:09:37 PM PDT 24 |
29996100 ps |
| T1080 |
/workspace/coverage/default/33.flash_ctrl_rw_evict.237248567 |
|
|
Jul 30 05:08:02 PM PDT 24 |
Jul 30 05:08:32 PM PDT 24 |
240674400 ps |
| T1081 |
/workspace/coverage/default/2.flash_ctrl_smoke.3844315893 |
|
|
Jul 30 04:59:32 PM PDT 24 |
Jul 30 05:01:59 PM PDT 24 |
100984100 ps |
| T164 |
/workspace/coverage/default/2.flash_ctrl_phy_arb_redun.2727223946 |
|
|
Jul 30 05:00:00 PM PDT 24 |
Jul 30 05:00:18 PM PDT 24 |
807198300 ps |
| T1082 |
/workspace/coverage/default/1.flash_ctrl_rw_derr.3347144540 |
|
|
Jul 30 04:59:27 PM PDT 24 |
Jul 30 05:03:23 PM PDT 24 |
11458821200 ps |
| T1083 |
/workspace/coverage/default/1.flash_ctrl_error_prog_type.304085837 |
|
|
Jul 30 04:59:19 PM PDT 24 |
Jul 30 05:45:17 PM PDT 24 |
11454589900 ps |
| T1084 |
/workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.4250830780 |
|
|
Jul 30 05:06:56 PM PDT 24 |
Jul 30 05:10:58 PM PDT 24 |
19623685400 ps |
| T1085 |
/workspace/coverage/default/78.flash_ctrl_otp_reset.1495050711 |
|
|
Jul 30 05:09:52 PM PDT 24 |
Jul 30 05:12:07 PM PDT 24 |
88002600 ps |
| T431 |
/workspace/coverage/default/1.flash_ctrl_oversize_error.1023530675 |
|
|
Jul 30 04:59:22 PM PDT 24 |
Jul 30 05:02:05 PM PDT 24 |
4439636400 ps |
| T1086 |
/workspace/coverage/default/45.flash_ctrl_hw_sec_otp.2209687599 |
|
|
Jul 30 05:09:08 PM PDT 24 |
Jul 30 05:11:07 PM PDT 24 |
2706368900 ps |
| T1087 |
/workspace/coverage/default/15.flash_ctrl_phy_arb.387470877 |
|
|
Jul 30 05:04:42 PM PDT 24 |
Jul 30 05:11:03 PM PDT 24 |
757630400 ps |
| T1088 |
/workspace/coverage/default/72.flash_ctrl_otp_reset.2186372090 |
|
|
Jul 30 05:09:46 PM PDT 24 |
Jul 30 05:11:39 PM PDT 24 |
296259700 ps |
| T1089 |
/workspace/coverage/default/7.flash_ctrl_phy_arb.1230123261 |
|
|
Jul 30 05:01:59 PM PDT 24 |
Jul 30 05:08:28 PM PDT 24 |
5461740100 ps |
| T1090 |
/workspace/coverage/default/16.flash_ctrl_rw_evict.3094412543 |
|
|
Jul 30 05:05:07 PM PDT 24 |
Jul 30 05:05:40 PM PDT 24 |
86303000 ps |
| T1091 |
/workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.3261777823 |
|
|
Jul 30 05:01:23 PM PDT 24 |
Jul 30 05:04:30 PM PDT 24 |
41197513000 ps |
| T1092 |
/workspace/coverage/default/1.flash_ctrl_wo.3203771750 |
|
|
Jul 30 04:59:23 PM PDT 24 |
Jul 30 05:02:01 PM PDT 24 |
13693479200 ps |
| T1093 |
/workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.47607100 |
|
|
Jul 30 05:03:09 PM PDT 24 |
Jul 30 05:03:23 PM PDT 24 |
25611200 ps |
| T1094 |
/workspace/coverage/default/46.flash_ctrl_sec_info_access.3833974152 |
|
|
Jul 30 05:09:11 PM PDT 24 |
Jul 30 05:10:20 PM PDT 24 |
7074135900 ps |
| T1095 |
/workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.2773249830 |
|
|
Jul 30 05:06:21 PM PDT 24 |
Jul 30 05:09:11 PM PDT 24 |
16319792600 ps |
| T1096 |
/workspace/coverage/default/70.flash_ctrl_connect.3096861689 |
|
|
Jul 30 05:09:46 PM PDT 24 |
Jul 30 05:10:03 PM PDT 24 |
39369600 ps |
| T1097 |
/workspace/coverage/default/16.flash_ctrl_rw.2602281113 |
|
|
Jul 30 05:05:01 PM PDT 24 |
Jul 30 05:15:01 PM PDT 24 |
3271137600 ps |
| T1098 |
/workspace/coverage/default/19.flash_ctrl_smoke.3970639151 |
|
|
Jul 30 05:05:45 PM PDT 24 |
Jul 30 05:07:26 PM PDT 24 |
44893700 ps |
| T1099 |
/workspace/coverage/default/17.flash_ctrl_re_evict.90046607 |
|
|
Jul 30 05:05:23 PM PDT 24 |
Jul 30 05:05:56 PM PDT 24 |
116099100 ps |
| T1100 |
/workspace/coverage/default/0.flash_ctrl_sec_info_access.2305275542 |
|
|
Jul 30 04:59:11 PM PDT 24 |
Jul 30 05:00:38 PM PDT 24 |
4280726600 ps |
| T1101 |
/workspace/coverage/default/46.flash_ctrl_smoke.2003365738 |
|
|
Jul 30 05:09:06 PM PDT 24 |
Jul 30 05:12:24 PM PDT 24 |
37505100 ps |
| T1102 |
/workspace/coverage/default/2.flash_ctrl_connect.2306698594 |
|
|
Jul 30 04:59:56 PM PDT 24 |
Jul 30 05:00:10 PM PDT 24 |
28096100 ps |
| T1103 |
/workspace/coverage/default/1.flash_ctrl_derr_detect.1676325554 |
|
|
Jul 30 04:59:22 PM PDT 24 |
Jul 30 05:02:59 PM PDT 24 |
1863875400 ps |
| T1104 |
/workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.2618227173 |
|
|
Jul 30 05:03:01 PM PDT 24 |
Jul 30 05:06:08 PM PDT 24 |
23718638100 ps |
| T1105 |
/workspace/coverage/default/20.flash_ctrl_disable.2574368657 |
|
|
Jul 30 05:06:07 PM PDT 24 |
Jul 30 05:06:28 PM PDT 24 |
12420300 ps |
| T1106 |
/workspace/coverage/default/15.flash_ctrl_otp_reset.2768951156 |
|
|
Jul 30 05:04:41 PM PDT 24 |
Jul 30 05:06:56 PM PDT 24 |
73340100 ps |
| T1107 |
/workspace/coverage/default/27.flash_ctrl_disable.246540375 |
|
|
Jul 30 05:07:07 PM PDT 24 |
Jul 30 05:07:30 PM PDT 24 |
33146000 ps |
| T1108 |
/workspace/coverage/default/36.flash_ctrl_connect.1625832978 |
|
|
Jul 30 05:08:18 PM PDT 24 |
Jul 30 05:08:32 PM PDT 24 |
24866800 ps |
| T1109 |
/workspace/coverage/default/5.flash_ctrl_error_mp.1403251143 |
|
|
Jul 30 05:01:16 PM PDT 24 |
Jul 30 05:39:34 PM PDT 24 |
5391806200 ps |
| T1110 |
/workspace/coverage/default/64.flash_ctrl_connect.3576839029 |
|
|
Jul 30 05:09:39 PM PDT 24 |
Jul 30 05:09:55 PM PDT 24 |
50306000 ps |
| T1111 |
/workspace/coverage/default/17.flash_ctrl_rw.1713342475 |
|
|
Jul 30 05:05:19 PM PDT 24 |
Jul 30 05:12:47 PM PDT 24 |
12271128600 ps |
| T1112 |
/workspace/coverage/default/4.flash_ctrl_hw_sec_otp.3511965774 |
|
|
Jul 30 05:00:36 PM PDT 24 |
Jul 30 05:04:29 PM PDT 24 |
12151759800 ps |
| T1113 |
/workspace/coverage/default/1.flash_ctrl_error_prog_win.3434204146 |
|
|
Jul 30 04:59:22 PM PDT 24 |
Jul 30 05:13:19 PM PDT 24 |
782087700 ps |
| T1114 |
/workspace/coverage/default/71.flash_ctrl_connect.1185111301 |
|
|
Jul 30 05:09:45 PM PDT 24 |
Jul 30 05:09:58 PM PDT 24 |
29265800 ps |
| T1115 |
/workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.1896928329 |
|
|
Jul 30 05:08:00 PM PDT 24 |
Jul 30 05:11:50 PM PDT 24 |
37291389400 ps |
| T1116 |
/workspace/coverage/default/10.flash_ctrl_disable.2585813793 |
|
|
Jul 30 05:03:31 PM PDT 24 |
Jul 30 05:03:52 PM PDT 24 |
70351600 ps |
| T1117 |
/workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.1389186059 |
|
|
Jul 30 05:00:56 PM PDT 24 |
Jul 30 05:01:27 PM PDT 24 |
27969000 ps |
| T1118 |
/workspace/coverage/default/59.flash_ctrl_otp_reset.4194121592 |
|
|
Jul 30 05:09:33 PM PDT 24 |
Jul 30 05:11:46 PM PDT 24 |
41132100 ps |
| T1119 |
/workspace/coverage/default/31.flash_ctrl_sec_info_access.1345728852 |
|
|
Jul 30 05:07:41 PM PDT 24 |
Jul 30 05:08:56 PM PDT 24 |
2608952100 ps |
| T1120 |
/workspace/coverage/default/2.flash_ctrl_alert_test.710915358 |
|
|
Jul 30 05:00:03 PM PDT 24 |
Jul 30 05:00:20 PM PDT 24 |
301051300 ps |
| T1121 |
/workspace/coverage/default/5.flash_ctrl_prog_reset.2599519886 |
|
|
Jul 30 05:01:25 PM PDT 24 |
Jul 30 05:01:38 PM PDT 24 |
108748300 ps |
| T1122 |
/workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.3376220458 |
|
|
Jul 30 04:59:09 PM PDT 24 |
Jul 30 04:59:32 PM PDT 24 |
18692300 ps |
| T1123 |
/workspace/coverage/default/17.flash_ctrl_hw_rma_reset.1997805465 |
|
|
Jul 30 05:05:11 PM PDT 24 |
Jul 30 05:21:04 PM PDT 24 |
160179772900 ps |
| T1124 |
/workspace/coverage/default/10.flash_ctrl_hw_sec_otp.3340485684 |
|
|
Jul 30 05:03:16 PM PDT 24 |
Jul 30 05:04:18 PM PDT 24 |
5382926200 ps |
| T1125 |
/workspace/coverage/default/16.flash_ctrl_smoke.48544865 |
|
|
Jul 30 05:04:59 PM PDT 24 |
Jul 30 05:08:09 PM PDT 24 |
23395100 ps |
| T1126 |
/workspace/coverage/default/0.flash_ctrl_rd_buff_evict.303933683 |
|
|
Jul 30 04:59:03 PM PDT 24 |
Jul 30 05:00:57 PM PDT 24 |
3046411100 ps |
| T1127 |
/workspace/coverage/default/72.flash_ctrl_connect.735465829 |
|
|
Jul 30 05:09:46 PM PDT 24 |
Jul 30 05:10:03 PM PDT 24 |
20475900 ps |
| T1128 |
/workspace/coverage/default/5.flash_ctrl_ro_serr.3735807275 |
|
|
Jul 30 05:01:21 PM PDT 24 |
Jul 30 05:03:40 PM PDT 24 |
1014844000 ps |
| T1129 |
/workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.2576594371 |
|
|
Jul 30 05:02:07 PM PDT 24 |
Jul 30 05:06:37 PM PDT 24 |
12554232500 ps |
| T58 |
/workspace/coverage/default/0.flash_ctrl_phy_arb_redun.1563398304 |
|
|
Jul 30 04:59:17 PM PDT 24 |
Jul 30 04:59:36 PM PDT 24 |
715487700 ps |
| T1130 |
/workspace/coverage/default/1.flash_ctrl_phy_arb.2918749681 |
|
|
Jul 30 04:59:22 PM PDT 24 |
Jul 30 05:01:15 PM PDT 24 |
109734800 ps |
| T74 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.4149194048 |
|
|
Jul 30 06:27:11 PM PDT 24 |
Jul 30 06:28:26 PM PDT 24 |
3284652100 ps |
| T75 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3931649505 |
|
|
Jul 30 06:27:10 PM PDT 24 |
Jul 30 06:27:49 PM PDT 24 |
112623900 ps |
| T76 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2918051453 |
|
|
Jul 30 06:27:17 PM PDT 24 |
Jul 30 06:27:34 PM PDT 24 |
53092300 ps |
| T108 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3488225164 |
|
|
Jul 30 06:27:18 PM PDT 24 |
Jul 30 06:27:43 PM PDT 24 |
32886700 ps |
| T1131 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1611303483 |
|
|
Jul 30 06:27:13 PM PDT 24 |
Jul 30 06:27:26 PM PDT 24 |
26305200 ps |
| T1132 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2036443870 |
|
|
Jul 30 06:27:14 PM PDT 24 |
Jul 30 06:27:28 PM PDT 24 |
41833300 ps |
| T252 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1450453604 |
|
|
Jul 30 06:27:24 PM PDT 24 |
Jul 30 06:27:38 PM PDT 24 |
51852500 ps |
| T253 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1805258539 |
|
|
Jul 30 06:27:22 PM PDT 24 |
Jul 30 06:27:35 PM PDT 24 |
74466400 ps |
| T1133 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3718836459 |
|
|
Jul 30 06:27:13 PM PDT 24 |
Jul 30 06:27:29 PM PDT 24 |
41751800 ps |
| T109 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.480691749 |
|
|
Jul 30 06:27:13 PM PDT 24 |
Jul 30 06:27:30 PM PDT 24 |
152628900 ps |
| T1134 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3698208661 |
|
|
Jul 30 06:27:13 PM PDT 24 |
Jul 30 06:27:27 PM PDT 24 |
24743400 ps |
| T105 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1283925330 |
|
|
Jul 30 06:27:08 PM PDT 24 |
Jul 30 06:42:11 PM PDT 24 |
2714527200 ps |
| T247 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1161660885 |
|
|
Jul 30 06:27:23 PM PDT 24 |
Jul 30 06:27:42 PM PDT 24 |
61129500 ps |
| T239 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3762213813 |
|
|
Jul 30 06:27:23 PM PDT 24 |
Jul 30 06:27:40 PM PDT 24 |
32681200 ps |
| T1135 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.999562412 |
|
|
Jul 30 06:27:12 PM PDT 24 |
Jul 30 06:27:25 PM PDT 24 |
19005300 ps |
| T106 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.4241835880 |
|
|
Jul 30 06:27:22 PM PDT 24 |
Jul 30 06:34:56 PM PDT 24 |
373009400 ps |
| T287 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.439119152 |
|
|
Jul 30 06:27:10 PM PDT 24 |
Jul 30 06:28:13 PM PDT 24 |
5160261600 ps |
| T283 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1702106567 |
|
|
Jul 30 06:27:14 PM PDT 24 |
Jul 30 06:27:28 PM PDT 24 |
19386600 ps |
| T347 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2189170596 |
|
|
Jul 30 06:27:23 PM PDT 24 |
Jul 30 06:27:42 PM PDT 24 |
56350800 ps |
| T107 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.4243465362 |
|
|
Jul 30 06:27:17 PM PDT 24 |
Jul 30 06:27:36 PM PDT 24 |
101414100 ps |
| T348 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2560691465 |
|
|
Jul 30 06:27:25 PM PDT 24 |
Jul 30 06:27:39 PM PDT 24 |
35801900 ps |
| T350 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1010669081 |
|
|
Jul 30 06:27:24 PM PDT 24 |
Jul 30 06:27:37 PM PDT 24 |
23082200 ps |
| T288 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1418074408 |
|
|
Jul 30 06:27:13 PM PDT 24 |
Jul 30 06:27:30 PM PDT 24 |
138786200 ps |
| T256 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1383712161 |
|
|
Jul 30 06:27:16 PM PDT 24 |
Jul 30 06:27:46 PM PDT 24 |
50905400 ps |
| T349 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1134992245 |
|
|
Jul 30 06:27:27 PM PDT 24 |
Jul 30 06:27:41 PM PDT 24 |
14283300 ps |
| T1136 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1297780116 |
|
|
Jul 30 06:27:22 PM PDT 24 |
Jul 30 06:27:36 PM PDT 24 |
14909500 ps |
| T1137 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.195166196 |
|
|
Jul 30 06:27:21 PM PDT 24 |
Jul 30 06:27:37 PM PDT 24 |
18065600 ps |
| T1138 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1193332366 |
|
|
Jul 30 06:27:20 PM PDT 24 |
Jul 30 06:27:36 PM PDT 24 |
40413400 ps |
| T289 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3139237359 |
|
|
Jul 30 06:27:19 PM PDT 24 |
Jul 30 06:27:37 PM PDT 24 |
155282500 ps |
| T351 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2424985086 |
|
|
Jul 30 06:27:25 PM PDT 24 |
Jul 30 06:27:39 PM PDT 24 |
17629200 ps |
| T290 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2094880230 |
|
|
Jul 30 06:27:15 PM PDT 24 |
Jul 30 06:27:33 PM PDT 24 |
128811200 ps |
| T291 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2443975678 |
|
|
Jul 30 06:27:15 PM PDT 24 |
Jul 30 06:27:30 PM PDT 24 |
262931900 ps |
| T292 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1661408120 |
|
|
Jul 30 06:27:28 PM PDT 24 |
Jul 30 06:28:03 PM PDT 24 |
232447900 ps |
| T352 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.659233727 |
|
|
Jul 30 06:27:23 PM PDT 24 |
Jul 30 06:27:37 PM PDT 24 |
30411800 ps |
| T255 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2871605933 |
|
|
Jul 30 06:27:25 PM PDT 24 |
Jul 30 06:27:42 PM PDT 24 |
153464200 ps |
| T1139 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.4025855668 |
|
|
Jul 30 06:27:15 PM PDT 24 |
Jul 30 06:27:29 PM PDT 24 |
47143300 ps |
| T1140 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3072581030 |
|
|
Jul 30 06:27:17 PM PDT 24 |
Jul 30 06:27:32 PM PDT 24 |
35298300 ps |
| T1141 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1650877099 |
|
|
Jul 30 06:27:20 PM PDT 24 |
Jul 30 06:27:36 PM PDT 24 |
16734500 ps |
| T1142 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1309588113 |
|
|
Jul 30 06:27:27 PM PDT 24 |
Jul 30 06:27:40 PM PDT 24 |
15002200 ps |
| T243 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.4269596578 |
|
|
Jul 30 06:27:09 PM PDT 24 |
Jul 30 06:34:46 PM PDT 24 |
355416800 ps |
| T1143 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3579422019 |
|
|
Jul 30 06:27:21 PM PDT 24 |
Jul 30 06:27:37 PM PDT 24 |
63308100 ps |
| T267 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.536886601 |
|
|
Jul 30 06:27:18 PM PDT 24 |
Jul 30 06:27:35 PM PDT 24 |
157745000 ps |
| T279 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1003142768 |
|
|
Jul 30 06:27:15 PM PDT 24 |
Jul 30 06:27:32 PM PDT 24 |
171456400 ps |
| T1144 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3389092785 |
|
|
Jul 30 06:27:28 PM PDT 24 |
Jul 30 06:27:44 PM PDT 24 |
31278100 ps |
| T1145 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1727134630 |
|
|
Jul 30 06:27:23 PM PDT 24 |
Jul 30 06:27:39 PM PDT 24 |
16234200 ps |
| T311 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2451720449 |
|
|
Jul 30 06:27:14 PM PDT 24 |
Jul 30 06:28:01 PM PDT 24 |
1716921000 ps |
| T1146 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.286917999 |
|
|
Jul 30 06:27:21 PM PDT 24 |
Jul 30 06:27:37 PM PDT 24 |
27211900 ps |
| T293 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2427528880 |
|
|
Jul 30 06:27:11 PM PDT 24 |
Jul 30 06:27:27 PM PDT 24 |
97691600 ps |
| T1147 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3446308834 |
|
|
Jul 30 06:27:21 PM PDT 24 |
Jul 30 06:27:37 PM PDT 24 |
13456400 ps |
| T248 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1402037850 |
|
|
Jul 30 06:27:20 PM PDT 24 |
Jul 30 06:27:38 PM PDT 24 |
420035500 ps |
| T1148 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.4033696748 |
|
|
Jul 30 06:27:11 PM PDT 24 |
Jul 30 06:27:27 PM PDT 24 |
12052300 ps |
| T1149 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1726856048 |
|
|
Jul 30 06:27:22 PM PDT 24 |
Jul 30 06:27:35 PM PDT 24 |
11781600 ps |
| T280 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.665490684 |
|
|
Jul 30 06:27:19 PM PDT 24 |
Jul 30 06:42:18 PM PDT 24 |
808704300 ps |
| T1150 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1884411149 |
|
|
Jul 30 06:27:22 PM PDT 24 |
Jul 30 06:27:38 PM PDT 24 |
36317900 ps |
| T1151 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2572987680 |
|
|
Jul 30 06:27:18 PM PDT 24 |
Jul 30 06:27:32 PM PDT 24 |
69718000 ps |
| T1152 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.4064112348 |
|
|
Jul 30 06:27:26 PM PDT 24 |
Jul 30 06:27:39 PM PDT 24 |
110180000 ps |
| T257 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1067294584 |
|
|
Jul 30 06:27:16 PM PDT 24 |
Jul 30 06:42:36 PM PDT 24 |
3246929100 ps |
| T261 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2963168370 |
|
|
Jul 30 06:27:15 PM PDT 24 |
Jul 30 06:42:34 PM PDT 24 |
695023600 ps |
| T346 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3100721989 |
|
|
Jul 30 06:27:19 PM PDT 24 |
Jul 30 06:27:35 PM PDT 24 |
80573200 ps |
| T284 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1024592185 |
|
|
Jul 30 06:27:16 PM PDT 24 |
Jul 30 06:27:29 PM PDT 24 |
19853000 ps |
| T1153 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.322820885 |
|
|
Jul 30 06:27:24 PM PDT 24 |
Jul 30 06:27:43 PM PDT 24 |
16436600 ps |
| T1154 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.4040136010 |
|
|
Jul 30 06:27:28 PM PDT 24 |
Jul 30 06:27:42 PM PDT 24 |
26650300 ps |
| T1155 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.1766444246 |
|
|
Jul 30 06:27:25 PM PDT 24 |
Jul 30 06:27:39 PM PDT 24 |
158815800 ps |
| T262 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3509239265 |
|
|
Jul 30 06:27:13 PM PDT 24 |
Jul 30 06:27:30 PM PDT 24 |
24052100 ps |
| T251 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1707825815 |
|
|
Jul 30 06:27:12 PM PDT 24 |
Jul 30 06:27:28 PM PDT 24 |
33538300 ps |
| T1156 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.4005240027 |
|
|
Jul 30 06:27:10 PM PDT 24 |
Jul 30 06:27:24 PM PDT 24 |
120029900 ps |
| T1157 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.349698285 |
|
|
Jul 30 06:27:19 PM PDT 24 |
Jul 30 06:27:32 PM PDT 24 |
30373300 ps |
| T249 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3568568043 |
|
|
Jul 30 06:27:17 PM PDT 24 |
Jul 30 06:27:37 PM PDT 24 |
83806600 ps |
| T1158 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1418581850 |
|
|
Jul 30 06:27:17 PM PDT 24 |
Jul 30 06:27:31 PM PDT 24 |
30180600 ps |
| T269 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.308836950 |
|
|
Jul 30 06:27:25 PM PDT 24 |
Jul 30 06:33:54 PM PDT 24 |
182285500 ps |
| T1159 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.160889732 |
|
|
Jul 30 06:27:24 PM PDT 24 |
Jul 30 06:27:45 PM PDT 24 |
1556637500 ps |
| T1160 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.4065358674 |
|
|
Jul 30 06:27:21 PM PDT 24 |
Jul 30 06:27:34 PM PDT 24 |
21539700 ps |
| T1161 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3133465572 |
|
|
Jul 30 06:27:28 PM PDT 24 |
Jul 30 06:27:42 PM PDT 24 |
18330400 ps |
| T1162 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.616699011 |
|
|
Jul 30 06:27:21 PM PDT 24 |
Jul 30 06:27:35 PM PDT 24 |
16431500 ps |
| T1163 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1652636979 |
|
|
Jul 30 06:27:19 PM PDT 24 |
Jul 30 06:27:33 PM PDT 24 |
17249800 ps |
| T1164 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.32846624 |
|
|
Jul 30 06:27:26 PM PDT 24 |
Jul 30 06:33:51 PM PDT 24 |
232560000 ps |
| T260 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2597205422 |
|
|
Jul 30 06:27:20 PM PDT 24 |
Jul 30 06:34:55 PM PDT 24 |
680256900 ps |
| T394 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.1748958111 |
|
|
Jul 30 06:27:21 PM PDT 24 |
Jul 30 06:33:51 PM PDT 24 |
186563600 ps |
| T1165 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3991117294 |
|
|
Jul 30 06:27:14 PM PDT 24 |
Jul 30 06:27:34 PM PDT 24 |
812435600 ps |
| T1166 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.4019590061 |
|
|
Jul 30 06:27:21 PM PDT 24 |
Jul 30 06:27:34 PM PDT 24 |
22472200 ps |
| T1167 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.20030783 |
|
|
Jul 30 06:27:23 PM PDT 24 |
Jul 30 06:27:39 PM PDT 24 |
23550100 ps |
| T312 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.659689433 |
|
|
Jul 30 06:27:15 PM PDT 24 |
Jul 30 06:27:30 PM PDT 24 |
233834900 ps |
| T1168 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1038485246 |
|
|
Jul 30 06:27:15 PM PDT 24 |
Jul 30 06:27:31 PM PDT 24 |
74623600 ps |
| T1169 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.1450520517 |
|
|
Jul 30 06:27:29 PM PDT 24 |
Jul 30 06:27:43 PM PDT 24 |
48710600 ps |
| T1170 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.978522662 |
|
|
Jul 30 06:27:22 PM PDT 24 |
Jul 30 06:27:36 PM PDT 24 |
53242400 ps |
| T1171 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1086597165 |
|
|
Jul 30 06:27:24 PM PDT 24 |
Jul 30 06:27:40 PM PDT 24 |
64156200 ps |
| T254 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.4114278160 |
|
|
Jul 30 06:27:23 PM PDT 24 |
Jul 30 06:27:39 PM PDT 24 |
50681300 ps |
| T1172 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.783107765 |
|
|
Jul 30 06:27:20 PM PDT 24 |
Jul 30 06:27:34 PM PDT 24 |
55889200 ps |
| T1173 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2927435591 |
|
|
Jul 30 06:27:21 PM PDT 24 |
Jul 30 06:27:37 PM PDT 24 |
18093000 ps |
| T313 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.4051871495 |
|
|
Jul 30 06:27:25 PM PDT 24 |
Jul 30 06:35:10 PM PDT 24 |
460475500 ps |
| T1174 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3583796804 |
|
|
Jul 30 06:27:16 PM PDT 24 |
Jul 30 06:27:29 PM PDT 24 |
17787800 ps |
| T388 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2584326184 |
|
|
Jul 30 06:27:11 PM PDT 24 |
Jul 30 06:34:54 PM PDT 24 |
1567691400 ps |
| T1175 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.3191843916 |
|
|
Jul 30 06:27:26 PM PDT 24 |
Jul 30 06:27:40 PM PDT 24 |
21713500 ps |
| T1176 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2309892962 |
|
|
Jul 30 06:27:21 PM PDT 24 |
Jul 30 06:27:35 PM PDT 24 |
36885000 ps |
| T250 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2930205874 |
|
|
Jul 30 06:27:14 PM PDT 24 |
Jul 30 06:27:32 PM PDT 24 |
169642000 ps |
| T1177 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2857303592 |
|
|
Jul 30 06:27:10 PM PDT 24 |
Jul 30 06:27:25 PM PDT 24 |
28982200 ps |
| T1178 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.510199810 |
|
|
Jul 30 06:27:25 PM PDT 24 |
Jul 30 06:27:38 PM PDT 24 |
34186000 ps |
| T1179 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.752212661 |
|
|
Jul 30 06:27:11 PM PDT 24 |
Jul 30 06:27:30 PM PDT 24 |
91253100 ps |
| T314 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1797311914 |
|
|
Jul 30 06:27:17 PM PDT 24 |
Jul 30 06:27:34 PM PDT 24 |
119025000 ps |
| T1180 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1286474559 |
|
|
Jul 30 06:27:25 PM PDT 24 |
Jul 30 06:27:42 PM PDT 24 |
83261500 ps |
| T1181 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3473575664 |
|
|
Jul 30 06:27:20 PM PDT 24 |
Jul 30 06:27:37 PM PDT 24 |
69901700 ps |
| T263 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.244756989 |
|
|
Jul 30 06:27:26 PM PDT 24 |
Jul 30 06:27:45 PM PDT 24 |
63119000 ps |
| T1182 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3481780739 |
|
|
Jul 30 06:27:09 PM PDT 24 |
Jul 30 06:27:40 PM PDT 24 |
18569200 ps |
| T1183 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.195665060 |
|
|
Jul 30 06:27:20 PM PDT 24 |
Jul 30 06:27:34 PM PDT 24 |
69642800 ps |
| T1184 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3813871121 |
|
|
Jul 30 06:27:16 PM PDT 24 |
Jul 30 06:27:33 PM PDT 24 |
512303400 ps |
| T315 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1968345641 |
|
|
Jul 30 06:27:24 PM PDT 24 |
Jul 30 06:27:41 PM PDT 24 |
111824000 ps |
| T1185 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2310409192 |
|
|
Jul 30 06:27:17 PM PDT 24 |
Jul 30 06:27:33 PM PDT 24 |
14891600 ps |
| T1186 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2744925685 |
|
|
Jul 30 06:27:14 PM PDT 24 |
Jul 30 06:27:28 PM PDT 24 |
34439700 ps |
| T316 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1932044276 |
|
|
Jul 30 06:27:23 PM PDT 24 |
Jul 30 06:27:41 PM PDT 24 |
461408900 ps |
| T1187 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.531421364 |
|
|
Jul 30 06:27:23 PM PDT 24 |
Jul 30 06:27:37 PM PDT 24 |
48175800 ps |
| T317 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2258003534 |
|
|
Jul 30 06:27:23 PM PDT 24 |
Jul 30 06:27:40 PM PDT 24 |
463051200 ps |
| T1188 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1374124526 |
|
|
Jul 30 06:27:19 PM PDT 24 |
Jul 30 06:27:32 PM PDT 24 |
17915300 ps |
| T318 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2244103792 |
|
|
Jul 30 06:27:10 PM PDT 24 |
Jul 30 06:27:30 PM PDT 24 |
213541100 ps |
| T1189 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2991260104 |
|
|
Jul 30 06:27:28 PM PDT 24 |
Jul 30 06:27:46 PM PDT 24 |
29658100 ps |
| T1190 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1214034512 |
|
|
Jul 30 06:27:16 PM PDT 24 |
Jul 30 06:27:30 PM PDT 24 |
26906800 ps |
| T1191 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.3825517309 |
|
|
Jul 30 06:27:15 PM PDT 24 |
Jul 30 06:27:29 PM PDT 24 |
327207200 ps |
| T1192 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1123192026 |
|
|
Jul 30 06:27:18 PM PDT 24 |
Jul 30 06:27:33 PM PDT 24 |
14234000 ps |
| T1193 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.813915721 |
|
|
Jul 30 06:27:09 PM PDT 24 |
Jul 30 06:27:27 PM PDT 24 |
212401300 ps |
| T1194 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3460697228 |
|
|
Jul 30 06:27:10 PM PDT 24 |
Jul 30 06:27:24 PM PDT 24 |
64705400 ps |
| T285 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.324684763 |
|
|
Jul 30 06:27:09 PM PDT 24 |
Jul 30 06:27:23 PM PDT 24 |
28283900 ps |
| T1195 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.444933732 |
|
|
Jul 30 06:27:19 PM PDT 24 |
Jul 30 06:27:33 PM PDT 24 |
25633000 ps |
| T1196 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.452707950 |
|
|
Jul 30 06:27:20 PM PDT 24 |
Jul 30 06:27:36 PM PDT 24 |
13642400 ps |
| T1197 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.4166289491 |
|
|
Jul 30 06:27:14 PM PDT 24 |
Jul 30 06:27:27 PM PDT 24 |
34645000 ps |
| T1198 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2398973008 |
|
|
Jul 30 06:27:16 PM PDT 24 |
Jul 30 06:27:30 PM PDT 24 |
30916000 ps |
| T1199 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3766953778 |
|
|
Jul 30 06:27:13 PM PDT 24 |
Jul 30 06:27:32 PM PDT 24 |
287305800 ps |
| T1200 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3089419825 |
|
|
Jul 30 06:27:28 PM PDT 24 |
Jul 30 06:27:47 PM PDT 24 |
189420800 ps |
| T319 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1386803883 |
|
|
Jul 30 06:27:19 PM PDT 24 |
Jul 30 06:27:40 PM PDT 24 |
217275800 ps |
| T1201 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.4164660204 |
|
|
Jul 30 06:27:18 PM PDT 24 |
Jul 30 06:27:37 PM PDT 24 |
39440400 ps |
| T1202 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1589951433 |
|
|
Jul 30 06:27:22 PM PDT 24 |
Jul 30 06:27:41 PM PDT 24 |
313766200 ps |
| T1203 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3450168665 |
|
|
Jul 30 06:27:16 PM PDT 24 |
Jul 30 06:27:30 PM PDT 24 |
15519200 ps |
| T1204 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1832174846 |
|
|
Jul 30 06:27:08 PM PDT 24 |
Jul 30 06:27:38 PM PDT 24 |
224388500 ps |
| T1205 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.3514066486 |
|
|
Jul 30 06:27:15 PM PDT 24 |
Jul 30 06:27:28 PM PDT 24 |
64497900 ps |
| T264 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1523099297 |
|
|
Jul 30 06:27:16 PM PDT 24 |
Jul 30 06:27:35 PM PDT 24 |
108267900 ps |
| T320 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2090634376 |
|
|
Jul 30 06:27:08 PM PDT 24 |
Jul 30 06:27:29 PM PDT 24 |
1025569600 ps |
| T389 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.295122135 |
|
|
Jul 30 06:27:10 PM PDT 24 |
Jul 30 06:34:52 PM PDT 24 |
1373375100 ps |
| T1206 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.83860637 |
|
|
Jul 30 06:27:24 PM PDT 24 |
Jul 30 06:27:42 PM PDT 24 |
425452800 ps |
| T1207 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2136625470 |
|
|
Jul 30 06:27:14 PM PDT 24 |
Jul 30 06:27:55 PM PDT 24 |
3603581400 ps |
| T1208 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.4248438016 |
|
|
Jul 30 06:27:23 PM PDT 24 |
Jul 30 06:27:57 PM PDT 24 |
124524000 ps |
| T1209 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.622110148 |
|
|
Jul 30 06:27:10 PM PDT 24 |
Jul 30 06:27:50 PM PDT 24 |
3070763600 ps |
| T1210 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2225868520 |
|
|
Jul 30 06:27:20 PM PDT 24 |
Jul 30 06:28:37 PM PDT 24 |
2197396000 ps |
| T392 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1318798078 |
|
|
Jul 30 06:27:13 PM PDT 24 |
Jul 30 06:34:48 PM PDT 24 |
419743700 ps |
| T1211 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.4207096100 |
|
|
Jul 30 06:27:13 PM PDT 24 |
Jul 30 06:27:32 PM PDT 24 |
80785000 ps |
| T258 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1900844083 |
|
|
Jul 30 06:27:11 PM PDT 24 |
Jul 30 06:27:31 PM PDT 24 |
688160000 ps |
| T1212 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3519473693 |
|
|
Jul 30 06:27:08 PM PDT 24 |
Jul 30 06:27:21 PM PDT 24 |
14998500 ps |
| T1213 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.4141390318 |
|
|
Jul 30 06:27:22 PM PDT 24 |
Jul 30 06:27:39 PM PDT 24 |
44869400 ps |
| T1214 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3252178818 |
|
|
Jul 30 06:27:20 PM PDT 24 |
Jul 30 06:27:34 PM PDT 24 |
49229100 ps |
| T259 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3360383228 |
|
|
Jul 30 06:27:09 PM PDT 24 |
Jul 30 06:27:29 PM PDT 24 |
218570000 ps |
| T1215 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2430090712 |
|
|
Jul 30 06:27:13 PM PDT 24 |
Jul 30 06:27:31 PM PDT 24 |
37535600 ps |
| T1216 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2454395038 |
|
|
Jul 30 06:27:14 PM PDT 24 |
Jul 30 06:27:31 PM PDT 24 |
334408500 ps |
| T1217 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.2124242161 |
|
|
Jul 30 06:27:32 PM PDT 24 |
Jul 30 06:27:46 PM PDT 24 |
27409200 ps |
| T1218 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3912340808 |
|
|
Jul 30 06:27:17 PM PDT 24 |
Jul 30 06:27:31 PM PDT 24 |
36504700 ps |
| T1219 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3159115790 |
|
|
Jul 30 06:27:18 PM PDT 24 |
Jul 30 06:27:32 PM PDT 24 |
26538900 ps |
| T1220 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.184424747 |
|
|
Jul 30 06:27:19 PM PDT 24 |
Jul 30 06:28:27 PM PDT 24 |
1762407600 ps |
| T286 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2521416743 |
|
|
Jul 30 06:27:14 PM PDT 24 |
Jul 30 06:27:28 PM PDT 24 |
16617400 ps |
| T1221 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.44731715 |
|
|
Jul 30 06:27:19 PM PDT 24 |
Jul 30 06:27:35 PM PDT 24 |
175152100 ps |
| T1222 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1577726864 |
|
|
Jul 30 06:27:18 PM PDT 24 |
Jul 30 06:27:32 PM PDT 24 |
25942400 ps |
| T1223 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2310868308 |
|
|
Jul 30 06:27:24 PM PDT 24 |
Jul 30 06:27:43 PM PDT 24 |
156524400 ps |
| T1224 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3521855411 |
|
|
Jul 30 06:27:17 PM PDT 24 |
Jul 30 06:27:31 PM PDT 24 |
55122500 ps |
| T1225 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.169386482 |
|
|
Jul 30 06:27:13 PM PDT 24 |
Jul 30 06:27:31 PM PDT 24 |
125348600 ps |
| T282 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3417398753 |
|
|
Jul 30 06:27:15 PM PDT 24 |
Jul 30 06:27:29 PM PDT 24 |
70107800 ps |
| T1226 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2842662260 |
|
|
Jul 30 06:27:18 PM PDT 24 |
Jul 30 06:27:31 PM PDT 24 |
17897300 ps |
| T1227 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.369819042 |
|
|
Jul 30 06:27:15 PM PDT 24 |
Jul 30 06:27:32 PM PDT 24 |
73919400 ps |
| T1228 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1738271374 |
|
|
Jul 30 06:27:14 PM PDT 24 |
Jul 30 06:27:30 PM PDT 24 |
11794800 ps |
| T1229 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.874154331 |
|
|
Jul 30 06:27:11 PM PDT 24 |
Jul 30 06:27:56 PM PDT 24 |
5718170400 ps |
| T1230 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.191263361 |
|
|
Jul 30 06:27:09 PM PDT 24 |
Jul 30 06:27:25 PM PDT 24 |
30891900 ps |
| T1231 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2606297652 |
|
|
Jul 30 06:27:21 PM PDT 24 |
Jul 30 06:27:34 PM PDT 24 |
27923300 ps |
| T1232 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1663471009 |
|
|
Jul 30 06:27:18 PM PDT 24 |
Jul 30 06:27:34 PM PDT 24 |
123905600 ps |
| T1233 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.863130193 |
|
|
Jul 30 06:27:19 PM PDT 24 |
Jul 30 06:27:34 PM PDT 24 |
65681200 ps |
| T1234 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.4054986258 |
|
|
Jul 30 06:27:19 PM PDT 24 |
Jul 30 06:27:35 PM PDT 24 |
23154100 ps |
| T1235 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3666106322 |
|
|
Jul 30 06:27:34 PM PDT 24 |
Jul 30 06:27:48 PM PDT 24 |
58219800 ps |
| T1236 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1822000639 |
|
|
Jul 30 06:27:16 PM PDT 24 |
Jul 30 06:27:30 PM PDT 24 |
20820700 ps |
| T1237 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2599246015 |
|
|
Jul 30 06:27:17 PM PDT 24 |
Jul 30 06:27:31 PM PDT 24 |
28912100 ps |
| T1238 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.868742144 |
|
|
Jul 30 06:27:20 PM PDT 24 |
Jul 30 06:27:36 PM PDT 24 |
27506100 ps |
| T1239 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1966448598 |
|
|
Jul 30 06:27:20 PM PDT 24 |
Jul 30 06:27:34 PM PDT 24 |
257469300 ps |
| T1240 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3640061843 |
|
|
Jul 30 06:27:19 PM PDT 24 |
Jul 30 06:27:33 PM PDT 24 |
20078200 ps |
| T266 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2860557380 |
|
|
Jul 30 06:27:22 PM PDT 24 |
Jul 30 06:27:38 PM PDT 24 |
306080000 ps |
| T1241 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.50996695 |
|
|
Jul 30 06:27:14 PM PDT 24 |
Jul 30 06:27:30 PM PDT 24 |
47656700 ps |
| T1242 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.985330152 |
|
|
Jul 30 06:27:26 PM PDT 24 |
Jul 30 06:27:42 PM PDT 24 |
307424400 ps |
| T1243 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.2604353614 |
|
|
Jul 30 06:27:20 PM PDT 24 |
Jul 30 06:27:39 PM PDT 24 |
16599200 ps |
| T1244 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2694671000 |
|
|
Jul 30 06:27:14 PM PDT 24 |
Jul 30 06:27:33 PM PDT 24 |
87284100 ps |
| T1245 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3823307682 |
|
|
Jul 30 06:27:12 PM PDT 24 |
Jul 30 06:27:26 PM PDT 24 |
12811600 ps |
| T1246 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2471975368 |
|
|
Jul 30 06:27:24 PM PDT 24 |
Jul 30 06:27:40 PM PDT 24 |
12692800 ps |
| T386 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2102139358 |
|
|
Jul 30 06:27:22 PM PDT 24 |
Jul 30 06:42:21 PM PDT 24 |
642127800 ps |
| T1247 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.244102879 |
|
|
Jul 30 06:27:25 PM PDT 24 |
Jul 30 06:27:52 PM PDT 24 |
31115600 ps |
| T1248 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2064832001 |
|
|
Jul 30 06:27:17 PM PDT 24 |
Jul 30 06:27:32 PM PDT 24 |
45146700 ps |
| T1249 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3569444414 |
|
|
Jul 30 06:27:25 PM PDT 24 |
Jul 30 06:27:47 PM PDT 24 |
853978600 ps |
| T265 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1585146037 |
|
|
Jul 30 06:27:18 PM PDT 24 |
Jul 30 06:27:38 PM PDT 24 |
142874900 ps |
| T1250 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1718956480 |
|
|
Jul 30 06:27:14 PM PDT 24 |
Jul 30 06:27:45 PM PDT 24 |
20486200 ps |
| T1251 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.3185579062 |
|
|
Jul 30 06:27:24 PM PDT 24 |
Jul 30 06:27:38 PM PDT 24 |
20646500 ps |
| T1252 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.377968519 |
|
|
Jul 30 06:27:17 PM PDT 24 |
Jul 30 06:27:32 PM PDT 24 |
13698700 ps |
| T1253 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3097657806 |
|
|
Jul 30 06:27:22 PM PDT 24 |
Jul 30 06:27:39 PM PDT 24 |
46232900 ps |
| T1254 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.53807225 |
|
|
Jul 30 06:27:17 PM PDT 24 |
Jul 30 06:27:31 PM PDT 24 |
16698600 ps |
| T387 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1522523720 |
|
|
Jul 30 06:27:17 PM PDT 24 |
Jul 30 06:40:02 PM PDT 24 |
824822600 ps |