Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	271909	1		T1	2		T2	2		T3	1
all_values[1]	271909	1		T1	2		T2	2		T3	1
all_values[2]	271909	1		T1	2		T2	2		T3	1
all_values[3]	271909	1		T1	2		T2	2		T3	1
all_values[4]	271909	1		T1	2		T2	2		T3	1
all_values[5]	271909	1		T1	2		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	550281	1		T1	12		T2	12		T3	6
auto[1]	1081173	1		T31	4492		T32	5904		T25	1920

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	800627	1		T1	7		T2	7		T3	4
auto[1]	830827	1		T1	5		T2	5		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	271756	1		T1	2		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	153	1		T258	5		T259	6		T327	2
all_values[1]	auto[0]	auto[1]	271730	1		T1	2		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	179	1		T257	5		T258	1		T259	3
all_values[2]	auto[0]	auto[0]	1649	1		T1	2		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	56	1		T329	1		T332	1		T333	1
all_values[2]	auto[1]	auto[0]	270160	1		T31	1123		T32	1476		T25	480
all_values[2]	auto[1]	auto[1]	44	1		T259	2		T328	1		T327	1
all_values[3]	auto[0]	auto[0]	1649	1		T1	2		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	52	1		T340	2		T341	2		T258	2
all_values[3]	auto[1]	auto[0]	89924	1		T31	319		T32	1476		T25	240
all_values[3]	auto[1]	auto[1]	180284	1		T31	804		T25	240		T45	9045
all_values[4]	auto[0]	auto[0]	1165	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	542	1		T1	1		T2	1		T4	1
all_values[4]	auto[1]	auto[0]	164341	1		T31	721		T32	1		T25	240
all_values[4]	auto[1]	auto[1]	105861	1		T31	402		T32	1475		T25	240
all_values[5]	auto[0]	auto[0]	1588	1		T1	2		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	94	1		T47	1		T48	1		T49	1
all_values[5]	auto[1]	auto[0]	270151	1		T31	1123		T32	1476		T25	480
all_values[5]	auto[1]	auto[1]	76	1		T257	1		T259	2		T330	2