Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	236193	1		T1	1733		T4	17		T17	942
auto[FlashEraseBank]	262867	1		T1	1706		T2	2		T4	4

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	252227	1		T1	1285		T2	1		T4	5
auto[FlashOpProgram]	227288	1		T1	2154		T2	1		T4	5
auto[FlashOpErase]	15545	1		T4	11		T5	48		T8	4
auto[FlashOpInvalid]	4000	1		T22	200		T80	200		T162	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	252227	1		T1	1285		T2	1		T4	5
op[FlashOpProgram]	227288	1		T1	2154		T2	1		T4	5
op[FlashOpErase]	15545	1		T4	11		T5	48		T8	4
read_erase_read	556	1		T4	1		T8	1		T34	16
read_prog_read	796	1		T1	11		T4	1		T21	2

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	359469	1		T1	2877		T2	1		T4	20
auto[FlashPartInfo]	135525	1		T1	547		T2	1		T4	1
auto[FlashPartInfo1]	898	1		T6	1		T58	4		T25	38
auto[FlashPartInfo2]	3168	1		T1	15		T17	8		T19	10

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	183205	1		T1	941		T4	5		T21	177
auto[FlashPartData]	auto[FlashOpProgram]	168733	1		T1	1936		T2	1		T4	4
auto[FlashPartData]	auto[FlashOpErase]	3637	1		T4	11		T8	4		T22	99
auto[FlashPartData]	auto[FlashOpInvalid]	3894	1		T22	198		T80	190		T162	194
auto[FlashPartInfo]	auto[FlashOpRead]	66226	1		T1	337		T2	1		T5	107
auto[FlashPartInfo]	auto[FlashOpProgram]	57347	1		T1	210		T4	1		T17	206
auto[FlashPartInfo]	auto[FlashOpErase]	11876	1		T5	48		T22	1		T34	11
auto[FlashPartInfo]	auto[FlashOpInvalid]	76	1		T22	2		T80	6		T162	4
auto[FlashPartInfo1]	auto[FlashOpRead]	729	1		T6	1		T58	4		T25	38
auto[FlashPartInfo1]	auto[FlashOpProgram]	162	1		T68	32		T80	1		T70	32
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T80	1		T140	1		T141	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T80	2		T140	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	2067	1		T1	7		T6	6		T31	69
auto[FlashPartInfo2]	auto[FlashOpProgram]	1046	1		T1	8		T17	8		T19	10
auto[FlashPartInfo2]	auto[FlashOpErase]	29	1		T80	1		T162	1		T205	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	26	1		T80	2		T162	2		T164	2