Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	1	31	96.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	1	31	96.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30668	1		T4	9		T5	88		T22	400
auto[1]	41	1		T34	4		T345	4		T346	1
auto[2]	55	1		T136	4		T163	1		T345	13
auto[3]	223	1		T34	8		T37	10		T33	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7756	1		T4	2		T5	22		T22	100
evic_idx[1]	7753	1		T4	2		T5	22		T22	100
evic_idx[2]	7742	1		T4	2		T5	22		T22	100
evic_idx[3]	7736	1		T4	3		T5	22		T22	100

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30127	1		T5	88		T22	400		T34	15
evic_op[2]	330	1		T4	1		T24	1		T33	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	1	31	96.88	1

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0]]	[evic_op[2]]	[auto[1]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7473	1		T5	22		T22	100		T123	51
evic_idx[0]	evic_op[1]	auto[1]	11	1		T34	1		T345	2		T347	5
evic_idx[0]	evic_op[1]	auto[2]	6	1		T345	4		T348	1		T349	1
evic_idx[0]	evic_op[1]	auto[3]	55	1		T34	3		T37	3		T205	4
evic_idx[0]	evic_op[2]	auto[0]	68	1		T30	4		T147	1		T51	1
evic_idx[0]	evic_op[2]	auto[2]	4	1		T136	1		T350	1		T351	1
evic_idx[0]	evic_op[2]	auto[3]	6	1		T208	1		T352	1		T353	1
evic_idx[1]	evic_op[1]	auto[0]	7473	1		T5	22		T22	100		T34	1
evic_idx[1]	evic_op[1]	auto[1]	8	1		T34	2		T345	1		T347	2
evic_idx[1]	evic_op[1]	auto[2]	6	1		T345	4		T354	1		T349	1
evic_idx[1]	evic_op[1]	auto[3]	45	1		T34	2		T37	2		T205	2
evic_idx[1]	evic_op[2]	auto[0]	66	1		T28	1		T30	4		T51	1
evic_idx[1]	evic_op[2]	auto[1]	1	1		T115	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[2]	6	1		T136	2		T355	1		T356	1
evic_idx[1]	evic_op[2]	auto[3]	15	1		T46	1		T357	1		T358	1
evic_idx[2]	evic_op[1]	auto[0]	7472	1		T5	22		T22	100		T34	1
evic_idx[2]	evic_op[1]	auto[1]	8	1		T34	1		T345	1		T347	4
evic_idx[2]	evic_op[1]	auto[2]	6	1		T345	2		T348	1		T359	2
evic_idx[2]	evic_op[1]	auto[3]	40	1		T34	1		T37	2		T205	1
evic_idx[2]	evic_op[2]	auto[0]	64	1		T24	1		T30	4		T51	1
evic_idx[2]	evic_op[2]	auto[1]	3	1		T360	1		T115	1		T361	1
evic_idx[2]	evic_op[2]	auto[2]	5	1		T136	1		T163	1		T362	1
evic_idx[2]	evic_op[2]	auto[3]	12	1		T139	1		T208	1		T308	1
evic_idx[3]	evic_op[1]	auto[0]	7472	1		T5	22		T22	100		T34	1
evic_idx[3]	evic_op[1]	auto[1]	5	1		T347	3		T363	1		T364	1
evic_idx[3]	evic_op[1]	auto[2]	5	1		T345	3		T365	1		T349	1
evic_idx[3]	evic_op[1]	auto[3]	42	1		T34	2		T37	3		T205	1
evic_idx[3]	evic_op[2]	auto[0]	62	1		T4	1		T30	4		T51	1
evic_idx[3]	evic_op[2]	auto[1]	5	1		T346	1		T366	1		T115	1
evic_idx[3]	evic_op[2]	auto[2]	5	1		T367	1		T350	1		T368	1
evic_idx[3]	evic_op[2]	auto[3]	8	1		T33	1		T369	1		T370	1