Summary for Variable instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for instr_type_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others | 
4768 | 
1 | 
 | 
T53 | 
139 | 
 | 
T54 | 
67 | 
 | 
T55 | 
113 | 
| instr_types[0] | 
5453 | 
1 | 
 | 
T53 | 
132 | 
 | 
T54 | 
155 | 
 | 
T55 | 
253 | 
| instr_types[1] | 
4086817 | 
1 | 
 | 
T1 | 
41002 | 
 | 
T4 | 
258 | 
 | 
T8 | 
160 | 
Summary for Variable key_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for key_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
4095090 | 
1 | 
 | 
T1 | 
41002 | 
 | 
T4 | 
258 | 
 | 
T8 | 
160 | 
| auto[1] | 
1948 | 
1 | 
 | 
T53 | 
125 | 
 | 
T54 | 
161 | 
 | 
T55 | 
254 | 
Summary for Cross key_instr_cross
Samples crossed: key_cp instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
6 | 
0 | 
6 | 
100.00 | 
 | 
Automatically Generated Cross Bins for key_instr_cross
Bins
| key_cp | instr_type_cp | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
others | 
4425 | 
1 | 
 | 
T53 | 
126 | 
 | 
T54 | 
55 | 
 | 
T55 | 
60 | 
| auto[0] | 
instr_types[0] | 
4853 | 
1 | 
 | 
T53 | 
119 | 
 | 
T54 | 
93 | 
 | 
T55 | 
189 | 
| auto[0] | 
instr_types[1] | 
4085812 | 
1 | 
 | 
T1 | 
41002 | 
 | 
T4 | 
258 | 
 | 
T8 | 
160 | 
| auto[1] | 
others | 
343 | 
1 | 
 | 
T53 | 
13 | 
 | 
T54 | 
12 | 
 | 
T55 | 
53 | 
| auto[1] | 
instr_types[0] | 
600 | 
1 | 
 | 
T53 | 
13 | 
 | 
T54 | 
62 | 
 | 
T55 | 
64 | 
| auto[1] | 
instr_types[1] | 
1005 | 
1 | 
 | 
T53 | 
99 | 
 | 
T54 | 
87 | 
 | 
T55 | 
137 |