Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	9128	1		T279	2707		T334	1494		T335	2607
rd_lvl[2]	10910	1		T279	2317		T334	2379		T335	1723
rd_lvl[3]	17371	1		T45	4623		T203	626		T279	1220
rd_lvl[4]	33651	1		T45	4422		T203	640		T279	1362
rd_lvl[5]	8980	1		T203	65		T279	1264		T336	455
rd_lvl[6]	14920	1		T31	493		T203	320		T279	48
rd_lvl[7]	10526	1		T31	133		T222	1857		T203	207
rd_lvl[8]	12983	1		T222	1525		T203	58		T279	1233
rd_lvl[9]	8800	1		T31	83		T77	590		T279	1652
rd_lvl[10]	10263	1		T31	83		T77	1076		T203	2
rd_lvl[11]	7293	1		T25	175		T279	64		T281	580
rd_lvl[12]	10231	1		T25	33		T281	1078		T337	730
rd_lvl[13]	4676	1		T203	187		T43	39		T337	156
rd_lvl[14]	6589	1		T25	32		T43	16		T44	1303
rd_lvl[15]	3122	1		T44	375		T338	487		T339	229