Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	271909	1		T1	2		T2	2		T3	1
all_pins[1]	271909	1		T1	2		T2	2		T3	1
all_pins[2]	271909	1		T1	2		T2	2		T3	1
all_pins[3]	271909	1		T1	2		T2	2		T3	1
all_pins[4]	271909	1		T1	2		T2	2		T3	1
all_pins[5]	271909	1		T1	2		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1342218	1		T1	12		T2	12		T3	6
values[0x1]	289236	1		T31	1194		T32	1475		T25	480
transitions[0x0=>0x1]	263077	1		T31	1111		T32	1475		T25	480
transitions[0x1=>0x0]	263064	1		T31	1111		T32	1475		T25	480

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	271756	1		T1	2		T2	2		T3	1
all_pins[0]	values[0x1]	153	1		T258	5		T259	6		T327	2
all_pins[0]	transitions[0x0=>0x1]	67	1		T258	4		T259	5		T327	1
all_pins[0]	transitions[0x1=>0x0]	93	1		T257	5		T259	2		T328	1
all_pins[1]	values[0x0]	271730	1		T1	2		T2	2		T3	1
all_pins[1]	values[0x1]	179	1		T257	5		T258	1		T259	3
all_pins[1]	transitions[0x0=>0x1]	155	1		T257	5		T258	1		T259	2
all_pins[1]	transitions[0x1=>0x0]	3117	1		T338	1170		T371	872		T372	1055
all_pins[2]	values[0x0]	268768	1		T1	2		T2	2		T3	1
all_pins[2]	values[0x1]	3141	1		T338	1170		T371	872		T372	1055
all_pins[2]	transitions[0x0=>0x1]	28	1		T259	2		T329	1		T330	1
all_pins[2]	transitions[0x1=>0x0]	169557	1		T31	792		T25	240		T45	9045
all_pins[3]	values[0x0]	99239	1		T1	2		T2	2		T3	1
all_pins[3]	values[0x1]	172670	1		T31	792		T25	240		T45	9045
all_pins[3]	transitions[0x0=>0x1]	149792	1		T31	709		T25	240		T45	7796
all_pins[3]	transitions[0x1=>0x0]	90139	1		T31	319		T32	1475		T25	240
all_pins[4]	values[0x0]	158892	1		T1	2		T2	2		T3	1
all_pins[4]	values[0x1]	113017	1		T31	402		T32	1475		T25	240
all_pins[4]	transitions[0x0=>0x1]	113005	1		T31	402		T32	1475		T25	240
all_pins[4]	transitions[0x1=>0x0]	64	1		T257	1		T259	1		T330	2
all_pins[5]	values[0x0]	271833	1		T1	2		T2	2		T3	1
all_pins[5]	values[0x1]	76	1		T257	1		T259	2		T330	2
all_pins[5]	transitions[0x0=>0x1]	30	1		T257	1		T333	1		T331	1
all_pins[5]	transitions[0x1=>0x0]	94	1		T258	4		T259	4		T327	2