| T1079 |
/workspace/coverage/default/4.flash_ctrl_integrity.4228396771 |
|
|
Jul 31 05:05:23 PM PDT 24 |
Jul 31 05:14:33 PM PDT 24 |
27601643600 ps |
| T1080 |
/workspace/coverage/default/4.flash_ctrl_alert_test.2692873232 |
|
|
Jul 31 05:05:23 PM PDT 24 |
Jul 31 05:05:36 PM PDT 24 |
118204400 ps |
| T1081 |
/workspace/coverage/default/47.flash_ctrl_disable.2602606206 |
|
|
Jul 31 05:08:14 PM PDT 24 |
Jul 31 05:08:36 PM PDT 24 |
14309800 ps |
| T1082 |
/workspace/coverage/default/43.flash_ctrl_hw_sec_otp.1851321752 |
|
|
Jul 31 05:08:06 PM PDT 24 |
Jul 31 05:10:10 PM PDT 24 |
1467951900 ps |
| T1083 |
/workspace/coverage/default/10.flash_ctrl_ro.2847524311 |
|
|
Jul 31 05:05:52 PM PDT 24 |
Jul 31 05:08:06 PM PDT 24 |
1768938800 ps |
| T1084 |
/workspace/coverage/default/17.flash_ctrl_wo.2129740374 |
|
|
Jul 31 05:06:34 PM PDT 24 |
Jul 31 05:09:38 PM PDT 24 |
2154211700 ps |
| T1085 |
/workspace/coverage/default/16.flash_ctrl_alert_test.4026217478 |
|
|
Jul 31 05:06:32 PM PDT 24 |
Jul 31 05:06:46 PM PDT 24 |
89725500 ps |
| T1086 |
/workspace/coverage/default/0.flash_ctrl_phy_arb.929478213 |
|
|
Jul 31 05:04:46 PM PDT 24 |
Jul 31 05:08:45 PM PDT 24 |
53358100 ps |
| T1087 |
/workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.1568905623 |
|
|
Jul 31 05:05:14 PM PDT 24 |
Jul 31 05:05:44 PM PDT 24 |
39205900 ps |
| T1088 |
/workspace/coverage/default/18.flash_ctrl_mp_regions.209128442 |
|
|
Jul 31 05:06:38 PM PDT 24 |
Jul 31 05:10:33 PM PDT 24 |
17257973800 ps |
| T1089 |
/workspace/coverage/default/44.flash_ctrl_smoke.3856260635 |
|
|
Jul 31 05:08:07 PM PDT 24 |
Jul 31 05:11:04 PM PDT 24 |
122833100 ps |
| T1090 |
/workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.3182339999 |
|
|
Jul 31 05:05:47 PM PDT 24 |
Jul 31 05:06:01 PM PDT 24 |
46421400 ps |
| T1091 |
/workspace/coverage/default/27.flash_ctrl_rw_evict.3712610234 |
|
|
Jul 31 05:07:18 PM PDT 24 |
Jul 31 05:07:48 PM PDT 24 |
52334900 ps |
| T1092 |
/workspace/coverage/default/26.flash_ctrl_smoke.4091541316 |
|
|
Jul 31 05:07:15 PM PDT 24 |
Jul 31 05:09:19 PM PDT 24 |
145447300 ps |
| T359 |
/workspace/coverage/default/10.flash_ctrl_re_evict.1820660047 |
|
|
Jul 31 05:05:56 PM PDT 24 |
Jul 31 05:06:30 PM PDT 24 |
265260900 ps |
| T1093 |
/workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.1261262180 |
|
|
Jul 31 05:04:44 PM PDT 24 |
Jul 31 05:05:07 PM PDT 24 |
18666600 ps |
| T1094 |
/workspace/coverage/default/6.flash_ctrl_connect.586365933 |
|
|
Jul 31 05:05:17 PM PDT 24 |
Jul 31 05:05:31 PM PDT 24 |
17026200 ps |
| T1095 |
/workspace/coverage/default/22.flash_ctrl_hw_sec_otp.1728388041 |
|
|
Jul 31 05:07:01 PM PDT 24 |
Jul 31 05:10:30 PM PDT 24 |
5186030100 ps |
| T1096 |
/workspace/coverage/default/18.flash_ctrl_lcmgr_intg.2135436251 |
|
|
Jul 31 05:06:43 PM PDT 24 |
Jul 31 05:06:56 PM PDT 24 |
21039800 ps |
| T1097 |
/workspace/coverage/default/5.flash_ctrl_intr_rd.1980185651 |
|
|
Jul 31 05:05:33 PM PDT 24 |
Jul 31 05:08:57 PM PDT 24 |
6808940200 ps |
| T1098 |
/workspace/coverage/default/1.flash_ctrl_intr_rd.2641824255 |
|
|
Jul 31 05:04:54 PM PDT 24 |
Jul 31 05:07:28 PM PDT 24 |
700511400 ps |
| T1099 |
/workspace/coverage/default/54.flash_ctrl_otp_reset.4171420483 |
|
|
Jul 31 05:08:19 PM PDT 24 |
Jul 31 05:10:31 PM PDT 24 |
147198100 ps |
| T1100 |
/workspace/coverage/default/3.flash_ctrl_smoke.3248123771 |
|
|
Jul 31 05:04:59 PM PDT 24 |
Jul 31 05:07:24 PM PDT 24 |
51167000 ps |
| T1101 |
/workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.163166972 |
|
|
Jul 31 05:06:00 PM PDT 24 |
Jul 31 05:08:20 PM PDT 24 |
5941430300 ps |
| T1102 |
/workspace/coverage/default/0.flash_ctrl_rw_evict.3214122991 |
|
|
Jul 31 05:04:57 PM PDT 24 |
Jul 31 05:05:27 PM PDT 24 |
49361900 ps |
| T184 |
/workspace/coverage/default/2.flash_ctrl_rma_err.4071568193 |
|
|
Jul 31 05:05:21 PM PDT 24 |
Jul 31 05:21:04 PM PDT 24 |
80352334400 ps |
| T1103 |
/workspace/coverage/default/2.flash_ctrl_integrity.677662084 |
|
|
Jul 31 05:05:03 PM PDT 24 |
Jul 31 05:16:15 PM PDT 24 |
4316958600 ps |
| T1104 |
/workspace/coverage/default/5.flash_ctrl_connect.3340955075 |
|
|
Jul 31 05:05:32 PM PDT 24 |
Jul 31 05:05:45 PM PDT 24 |
56478900 ps |
| T1105 |
/workspace/coverage/default/24.flash_ctrl_otp_reset.1560998915 |
|
|
Jul 31 05:07:06 PM PDT 24 |
Jul 31 05:08:58 PM PDT 24 |
34126100 ps |
| T349 |
/workspace/coverage/default/17.flash_ctrl_re_evict.464275692 |
|
|
Jul 31 05:06:33 PM PDT 24 |
Jul 31 05:07:05 PM PDT 24 |
953302600 ps |
| T1106 |
/workspace/coverage/default/46.flash_ctrl_alert_test.3365653343 |
|
|
Jul 31 05:08:18 PM PDT 24 |
Jul 31 05:08:33 PM PDT 24 |
197324300 ps |
| T1107 |
/workspace/coverage/default/21.flash_ctrl_hw_sec_otp.687984054 |
|
|
Jul 31 05:06:54 PM PDT 24 |
Jul 31 05:10:46 PM PDT 24 |
17009389500 ps |
| T1108 |
/workspace/coverage/default/28.flash_ctrl_otp_reset.1013275406 |
|
|
Jul 31 05:07:22 PM PDT 24 |
Jul 31 05:09:33 PM PDT 24 |
85387100 ps |
| T1109 |
/workspace/coverage/default/24.flash_ctrl_prog_reset.3837920167 |
|
|
Jul 31 05:07:05 PM PDT 24 |
Jul 31 05:07:19 PM PDT 24 |
38314700 ps |
| T1110 |
/workspace/coverage/default/16.flash_ctrl_hw_rma_reset.3054243870 |
|
|
Jul 31 05:06:29 PM PDT 24 |
Jul 31 05:21:11 PM PDT 24 |
50130425200 ps |
| T1111 |
/workspace/coverage/default/4.flash_ctrl_error_mp.3957588665 |
|
|
Jul 31 05:05:26 PM PDT 24 |
Jul 31 05:42:04 PM PDT 24 |
16224647300 ps |
| T1112 |
/workspace/coverage/default/15.flash_ctrl_connect.3342205184 |
|
|
Jul 31 05:06:28 PM PDT 24 |
Jul 31 05:06:42 PM PDT 24 |
27010700 ps |
| T1113 |
/workspace/coverage/default/6.flash_ctrl_error_mp.1182383214 |
|
|
Jul 31 05:05:21 PM PDT 24 |
Jul 31 05:42:13 PM PDT 24 |
12968667000 ps |
| T1114 |
/workspace/coverage/default/13.flash_ctrl_smoke.3076850977 |
|
|
Jul 31 05:06:07 PM PDT 24 |
Jul 31 05:08:12 PM PDT 24 |
25296900 ps |
| T1115 |
/workspace/coverage/default/4.flash_ctrl_lcmgr_intg.3711694782 |
|
|
Jul 31 05:05:17 PM PDT 24 |
Jul 31 05:05:30 PM PDT 24 |
27061000 ps |
| T1116 |
/workspace/coverage/default/9.flash_ctrl_smoke.1575332456 |
|
|
Jul 31 05:05:43 PM PDT 24 |
Jul 31 05:08:36 PM PDT 24 |
56522100 ps |
| T1117 |
/workspace/coverage/default/0.flash_ctrl_write_word_sweep.796089595 |
|
|
Jul 31 05:04:44 PM PDT 24 |
Jul 31 05:05:00 PM PDT 24 |
152292700 ps |
| T1118 |
/workspace/coverage/default/39.flash_ctrl_disable.2995316934 |
|
|
Jul 31 05:08:06 PM PDT 24 |
Jul 31 05:08:28 PM PDT 24 |
40714600 ps |
| T1119 |
/workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.2074398116 |
|
|
Jul 31 05:04:59 PM PDT 24 |
Jul 31 05:05:31 PM PDT 24 |
51903700 ps |
| T1120 |
/workspace/coverage/default/48.flash_ctrl_otp_reset.2795278387 |
|
|
Jul 31 05:08:20 PM PDT 24 |
Jul 31 05:10:35 PM PDT 24 |
74841800 ps |
| T91 |
/workspace/coverage/default/1.flash_ctrl_mid_op_rst.2121254186 |
|
|
Jul 31 05:05:01 PM PDT 24 |
Jul 31 05:06:11 PM PDT 24 |
3949443500 ps |
| T1121 |
/workspace/coverage/default/3.flash_ctrl_fetch_code.371202416 |
|
|
Jul 31 05:05:09 PM PDT 24 |
Jul 31 05:05:38 PM PDT 24 |
1970516800 ps |
| T1122 |
/workspace/coverage/default/59.flash_ctrl_connect.500582016 |
|
|
Jul 31 05:08:19 PM PDT 24 |
Jul 31 05:08:35 PM PDT 24 |
13066400 ps |
| T1123 |
/workspace/coverage/default/42.flash_ctrl_disable.2435598997 |
|
|
Jul 31 05:08:19 PM PDT 24 |
Jul 31 05:08:41 PM PDT 24 |
10938200 ps |
| T1124 |
/workspace/coverage/default/26.flash_ctrl_prog_reset.4129286561 |
|
|
Jul 31 05:07:14 PM PDT 24 |
Jul 31 05:07:28 PM PDT 24 |
52825700 ps |
| T1125 |
/workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.3909159805 |
|
|
Jul 31 05:05:58 PM PDT 24 |
Jul 31 05:09:05 PM PDT 24 |
10019366800 ps |
| T1126 |
/workspace/coverage/default/8.flash_ctrl_fetch_code.3547633275 |
|
|
Jul 31 05:05:35 PM PDT 24 |
Jul 31 05:05:59 PM PDT 24 |
121525900 ps |
| T1127 |
/workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.2249677983 |
|
|
Jul 31 05:06:34 PM PDT 24 |
Jul 31 05:08:50 PM PDT 24 |
18796528300 ps |
| T1128 |
/workspace/coverage/default/0.flash_ctrl_sec_info_access.3500532776 |
|
|
Jul 31 05:04:46 PM PDT 24 |
Jul 31 05:06:05 PM PDT 24 |
2291460000 ps |
| T1129 |
/workspace/coverage/default/10.flash_ctrl_intr_rd.2851117480 |
|
|
Jul 31 05:05:50 PM PDT 24 |
Jul 31 05:08:59 PM PDT 24 |
6366364000 ps |
| T318 |
/workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.920818323 |
|
|
Jul 31 05:06:34 PM PDT 24 |
Jul 31 05:06:48 PM PDT 24 |
15842900 ps |
| T1130 |
/workspace/coverage/default/4.flash_ctrl_error_prog_type.4051863094 |
|
|
Jul 31 05:05:11 PM PDT 24 |
Jul 31 05:55:32 PM PDT 24 |
1496615900 ps |
| T257 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3648519693 |
|
|
Jul 31 07:30:53 PM PDT 24 |
Jul 31 07:31:06 PM PDT 24 |
14707900 ps |
| T71 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.697210777 |
|
|
Jul 31 07:30:24 PM PDT 24 |
Jul 31 07:30:38 PM PDT 24 |
36235600 ps |
| T258 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2792377520 |
|
|
Jul 31 07:31:03 PM PDT 24 |
Jul 31 07:31:16 PM PDT 24 |
18041300 ps |
| T259 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3688528093 |
|
|
Jul 31 07:31:15 PM PDT 24 |
Jul 31 07:31:29 PM PDT 24 |
14878600 ps |
| T72 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2238414049 |
|
|
Jul 31 07:30:23 PM PDT 24 |
Jul 31 07:38:00 PM PDT 24 |
553020100 ps |
| T73 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.4185360389 |
|
|
Jul 31 07:30:32 PM PDT 24 |
Jul 31 07:45:29 PM PDT 24 |
2159688700 ps |
| T244 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3362669491 |
|
|
Jul 31 07:30:41 PM PDT 24 |
Jul 31 07:30:56 PM PDT 24 |
71674500 ps |
| T126 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.4252541974 |
|
|
Jul 31 07:31:03 PM PDT 24 |
Jul 31 07:38:39 PM PDT 24 |
973206500 ps |
| T1131 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.4095217049 |
|
|
Jul 31 07:30:29 PM PDT 24 |
Jul 31 07:30:43 PM PDT 24 |
23308900 ps |
| T245 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2148299016 |
|
|
Jul 31 07:31:03 PM PDT 24 |
Jul 31 07:31:18 PM PDT 24 |
215544600 ps |
| T1132 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3672362560 |
|
|
Jul 31 07:30:22 PM PDT 24 |
Jul 31 07:30:38 PM PDT 24 |
44657800 ps |
| T328 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.378437526 |
|
|
Jul 31 07:30:29 PM PDT 24 |
Jul 31 07:30:43 PM PDT 24 |
26598200 ps |
| T1133 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2267397808 |
|
|
Jul 31 07:31:02 PM PDT 24 |
Jul 31 07:31:16 PM PDT 24 |
18871600 ps |
| T246 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1649990105 |
|
|
Jul 31 07:31:08 PM PDT 24 |
Jul 31 07:31:26 PM PDT 24 |
39783500 ps |
| T327 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1669630942 |
|
|
Jul 31 07:31:16 PM PDT 24 |
Jul 31 07:31:30 PM PDT 24 |
28399700 ps |
| T247 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1696142285 |
|
|
Jul 31 07:30:49 PM PDT 24 |
Jul 31 07:31:06 PM PDT 24 |
342800700 ps |
| T1134 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3766845904 |
|
|
Jul 31 07:30:41 PM PDT 24 |
Jul 31 07:30:55 PM PDT 24 |
45072700 ps |
| T329 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1694335946 |
|
|
Jul 31 07:31:25 PM PDT 24 |
Jul 31 07:31:39 PM PDT 24 |
53102000 ps |
| T213 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2294996684 |
|
|
Jul 31 07:30:50 PM PDT 24 |
Jul 31 07:37:19 PM PDT 24 |
832600500 ps |
| T210 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1465587890 |
|
|
Jul 31 07:30:30 PM PDT 24 |
Jul 31 07:30:47 PM PDT 24 |
99358000 ps |
| T214 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1877962751 |
|
|
Jul 31 07:30:43 PM PDT 24 |
Jul 31 07:38:25 PM PDT 24 |
681320200 ps |
| T248 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1550131680 |
|
|
Jul 31 07:30:26 PM PDT 24 |
Jul 31 07:31:17 PM PDT 24 |
1726816200 ps |
| T263 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.637092047 |
|
|
Jul 31 07:30:29 PM PDT 24 |
Jul 31 07:31:01 PM PDT 24 |
38173200 ps |
| T249 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1355934447 |
|
|
Jul 31 07:30:30 PM PDT 24 |
Jul 31 07:30:47 PM PDT 24 |
102883200 ps |
| T330 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.313776869 |
|
|
Jul 31 07:30:51 PM PDT 24 |
Jul 31 07:31:05 PM PDT 24 |
15388500 ps |
| T332 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.3227340563 |
|
|
Jul 31 07:30:43 PM PDT 24 |
Jul 31 07:30:57 PM PDT 24 |
25435000 ps |
| T211 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3103478635 |
|
|
Jul 31 07:30:52 PM PDT 24 |
Jul 31 07:31:10 PM PDT 24 |
172141600 ps |
| T431 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.903795299 |
|
|
Jul 31 07:30:43 PM PDT 24 |
Jul 31 07:31:21 PM PDT 24 |
27214600 ps |
| T233 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3615619704 |
|
|
Jul 31 07:30:52 PM PDT 24 |
Jul 31 07:37:15 PM PDT 24 |
357996000 ps |
| T1135 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3351815906 |
|
|
Jul 31 07:30:59 PM PDT 24 |
Jul 31 07:31:12 PM PDT 24 |
100503500 ps |
| T234 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.4226006707 |
|
|
Jul 31 07:30:42 PM PDT 24 |
Jul 31 07:38:14 PM PDT 24 |
1661066500 ps |
| T250 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.3976271431 |
|
|
Jul 31 07:31:02 PM PDT 24 |
Jul 31 07:31:23 PM PDT 24 |
611334600 ps |
| T333 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1073074126 |
|
|
Jul 31 07:31:16 PM PDT 24 |
Jul 31 07:31:30 PM PDT 24 |
49003600 ps |
| T251 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2808411097 |
|
|
Jul 31 07:31:03 PM PDT 24 |
Jul 31 07:31:20 PM PDT 24 |
122561800 ps |
| T331 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.271117912 |
|
|
Jul 31 07:31:15 PM PDT 24 |
Jul 31 07:31:29 PM PDT 24 |
53593600 ps |
| T1136 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3050451938 |
|
|
Jul 31 07:31:15 PM PDT 24 |
Jul 31 07:31:28 PM PDT 24 |
116971500 ps |
| T252 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2997063943 |
|
|
Jul 31 07:30:42 PM PDT 24 |
Jul 31 07:31:16 PM PDT 24 |
64502900 ps |
| T1137 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3742996359 |
|
|
Jul 31 07:30:41 PM PDT 24 |
Jul 31 07:30:57 PM PDT 24 |
32579000 ps |
| T1138 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1866500818 |
|
|
Jul 31 07:31:03 PM PDT 24 |
Jul 31 07:31:17 PM PDT 24 |
25190000 ps |
| T1139 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2982571899 |
|
|
Jul 31 07:31:04 PM PDT 24 |
Jul 31 07:31:18 PM PDT 24 |
12601700 ps |
| T1140 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.909791027 |
|
|
Jul 31 07:30:28 PM PDT 24 |
Jul 31 07:31:13 PM PDT 24 |
305850800 ps |
| T1141 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1150141514 |
|
|
Jul 31 07:30:29 PM PDT 24 |
Jul 31 07:30:42 PM PDT 24 |
37066100 ps |
| T1142 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1021840733 |
|
|
Jul 31 07:30:50 PM PDT 24 |
Jul 31 07:31:06 PM PDT 24 |
24413100 ps |
| T1143 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.3823755719 |
|
|
Jul 31 07:30:54 PM PDT 24 |
Jul 31 07:31:08 PM PDT 24 |
136482900 ps |
| T212 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3952119240 |
|
|
Jul 31 07:30:41 PM PDT 24 |
Jul 31 07:31:02 PM PDT 24 |
134922500 ps |
| T235 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.986537360 |
|
|
Jul 31 07:31:04 PM PDT 24 |
Jul 31 07:31:23 PM PDT 24 |
52047500 ps |
| T1144 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.4247839255 |
|
|
Jul 31 07:31:18 PM PDT 24 |
Jul 31 07:31:31 PM PDT 24 |
56121100 ps |
| T236 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2206373896 |
|
|
Jul 31 07:30:33 PM PDT 24 |
Jul 31 07:30:50 PM PDT 24 |
338139300 ps |
| T297 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.1165434398 |
|
|
Jul 31 07:30:32 PM PDT 24 |
Jul 31 07:31:11 PM PDT 24 |
178251400 ps |
| T1145 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1594856421 |
|
|
Jul 31 07:31:19 PM PDT 24 |
Jul 31 07:31:33 PM PDT 24 |
15095300 ps |
| T1146 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1055227211 |
|
|
Jul 31 07:31:21 PM PDT 24 |
Jul 31 07:31:35 PM PDT 24 |
49237200 ps |
| T237 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2829834702 |
|
|
Jul 31 07:31:03 PM PDT 24 |
Jul 31 07:31:22 PM PDT 24 |
100923500 ps |
| T238 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.1728524960 |
|
|
Jul 31 07:31:03 PM PDT 24 |
Jul 31 07:31:19 PM PDT 24 |
86323500 ps |
| T1147 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2476168582 |
|
|
Jul 31 07:30:30 PM PDT 24 |
Jul 31 07:30:43 PM PDT 24 |
31154600 ps |
| T1148 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3156827505 |
|
|
Jul 31 07:30:59 PM PDT 24 |
Jul 31 07:31:15 PM PDT 24 |
14060300 ps |
| T1149 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.4267505318 |
|
|
Jul 31 07:30:43 PM PDT 24 |
Jul 31 07:30:58 PM PDT 24 |
30956800 ps |
| T1150 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.798457128 |
|
|
Jul 31 07:31:02 PM PDT 24 |
Jul 31 07:31:20 PM PDT 24 |
335929000 ps |
| T1151 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.260645404 |
|
|
Jul 31 07:30:30 PM PDT 24 |
Jul 31 07:30:47 PM PDT 24 |
97881100 ps |
| T1152 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.4178720830 |
|
|
Jul 31 07:30:29 PM PDT 24 |
Jul 31 07:30:49 PM PDT 24 |
241599500 ps |
| T1153 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.435655712 |
|
|
Jul 31 07:31:15 PM PDT 24 |
Jul 31 07:31:29 PM PDT 24 |
98437200 ps |
| T1154 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3707008209 |
|
|
Jul 31 07:31:03 PM PDT 24 |
Jul 31 07:31:19 PM PDT 24 |
68662100 ps |
| T239 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1777551245 |
|
|
Jul 31 07:31:03 PM PDT 24 |
Jul 31 07:31:22 PM PDT 24 |
623036300 ps |
| T1155 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.4009569144 |
|
|
Jul 31 07:30:45 PM PDT 24 |
Jul 31 07:31:01 PM PDT 24 |
66359100 ps |
| T1156 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3648313656 |
|
|
Jul 31 07:30:50 PM PDT 24 |
Jul 31 07:31:06 PM PDT 24 |
17716500 ps |
| T298 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1688413259 |
|
|
Jul 31 07:30:57 PM PDT 24 |
Jul 31 07:31:32 PM PDT 24 |
206679000 ps |
| T240 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.931256452 |
|
|
Jul 31 07:30:30 PM PDT 24 |
Jul 31 07:30:44 PM PDT 24 |
26464300 ps |
| T1157 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1264923611 |
|
|
Jul 31 07:30:44 PM PDT 24 |
Jul 31 07:31:03 PM PDT 24 |
65551400 ps |
| T276 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3103130103 |
|
|
Jul 31 07:30:55 PM PDT 24 |
Jul 31 07:45:55 PM PDT 24 |
1103693800 ps |
| T299 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1734257367 |
|
|
Jul 31 07:30:32 PM PDT 24 |
Jul 31 07:30:54 PM PDT 24 |
239567300 ps |
| T273 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.80831769 |
|
|
Jul 31 07:30:49 PM PDT 24 |
Jul 31 07:37:15 PM PDT 24 |
460994000 ps |
| T300 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3784265734 |
|
|
Jul 31 07:30:21 PM PDT 24 |
Jul 31 07:31:13 PM PDT 24 |
3158601700 ps |
| T1158 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.516433835 |
|
|
Jul 31 07:30:24 PM PDT 24 |
Jul 31 07:30:38 PM PDT 24 |
52921900 ps |
| T1159 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.309455359 |
|
|
Jul 31 07:31:02 PM PDT 24 |
Jul 31 07:31:20 PM PDT 24 |
364871700 ps |
| T1160 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2589953429 |
|
|
Jul 31 07:30:23 PM PDT 24 |
Jul 31 07:30:39 PM PDT 24 |
31221900 ps |
| T1161 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.3295913450 |
|
|
Jul 31 07:31:25 PM PDT 24 |
Jul 31 07:31:39 PM PDT 24 |
42545400 ps |
| T1162 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2048084622 |
|
|
Jul 31 07:30:54 PM PDT 24 |
Jul 31 07:31:09 PM PDT 24 |
80411000 ps |
| T1163 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.4052004330 |
|
|
Jul 31 07:30:31 PM PDT 24 |
Jul 31 07:30:47 PM PDT 24 |
21388800 ps |
| T270 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2055363573 |
|
|
Jul 31 07:30:48 PM PDT 24 |
Jul 31 07:31:07 PM PDT 24 |
81072900 ps |
| T373 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.4195509108 |
|
|
Jul 31 07:30:30 PM PDT 24 |
Jul 31 07:38:07 PM PDT 24 |
412043700 ps |
| T1164 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2129968733 |
|
|
Jul 31 07:30:57 PM PDT 24 |
Jul 31 07:31:27 PM PDT 24 |
253006500 ps |
| T1165 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2029110582 |
|
|
Jul 31 07:30:40 PM PDT 24 |
Jul 31 07:31:20 PM PDT 24 |
1159302100 ps |
| T1166 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2905709363 |
|
|
Jul 31 07:31:01 PM PDT 24 |
Jul 31 07:31:15 PM PDT 24 |
47256000 ps |
| T301 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3585759534 |
|
|
Jul 31 07:30:48 PM PDT 24 |
Jul 31 07:31:04 PM PDT 24 |
225223800 ps |
| T302 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1765820513 |
|
|
Jul 31 07:31:02 PM PDT 24 |
Jul 31 07:31:33 PM PDT 24 |
452522700 ps |
| T269 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2259028144 |
|
|
Jul 31 07:31:03 PM PDT 24 |
Jul 31 07:31:22 PM PDT 24 |
330490000 ps |
| T377 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.784145131 |
|
|
Jul 31 07:31:01 PM PDT 24 |
Jul 31 07:38:39 PM PDT 24 |
372707100 ps |
| T267 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2365549828 |
|
|
Jul 31 07:31:03 PM PDT 24 |
Jul 31 07:31:21 PM PDT 24 |
289711100 ps |
| T241 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2523836630 |
|
|
Jul 31 07:30:31 PM PDT 24 |
Jul 31 07:30:45 PM PDT 24 |
52488500 ps |
| T1167 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.573867524 |
|
|
Jul 31 07:30:42 PM PDT 24 |
Jul 31 07:31:16 PM PDT 24 |
232314700 ps |
| T1168 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3173474510 |
|
|
Jul 31 07:31:16 PM PDT 24 |
Jul 31 07:31:30 PM PDT 24 |
59153200 ps |
| T1169 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3728880025 |
|
|
Jul 31 07:31:16 PM PDT 24 |
Jul 31 07:31:30 PM PDT 24 |
56148600 ps |
| T1170 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2048358031 |
|
|
Jul 31 07:31:01 PM PDT 24 |
Jul 31 07:31:15 PM PDT 24 |
15033600 ps |
| T1171 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.584033768 |
|
|
Jul 31 07:30:44 PM PDT 24 |
Jul 31 07:30:57 PM PDT 24 |
22667300 ps |
| T1172 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3904077249 |
|
|
Jul 31 07:30:40 PM PDT 24 |
Jul 31 07:30:54 PM PDT 24 |
53687400 ps |
| T303 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2483866291 |
|
|
Jul 31 07:30:44 PM PDT 24 |
Jul 31 07:31:01 PM PDT 24 |
229426200 ps |
| T271 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.462462537 |
|
|
Jul 31 07:31:03 PM PDT 24 |
Jul 31 07:31:22 PM PDT 24 |
729622600 ps |
| T1173 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1142385204 |
|
|
Jul 31 07:30:30 PM PDT 24 |
Jul 31 07:30:44 PM PDT 24 |
20650700 ps |
| T1174 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1288804285 |
|
|
Jul 31 07:30:40 PM PDT 24 |
Jul 31 07:31:19 PM PDT 24 |
646522000 ps |
| T274 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2990761694 |
|
|
Jul 31 07:30:44 PM PDT 24 |
Jul 31 07:38:20 PM PDT 24 |
888140500 ps |
| T1175 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1503884297 |
|
|
Jul 31 07:31:15 PM PDT 24 |
Jul 31 07:31:29 PM PDT 24 |
16431800 ps |
| T1176 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3630052975 |
|
|
Jul 31 07:31:04 PM PDT 24 |
Jul 31 07:31:17 PM PDT 24 |
13339500 ps |
| T1177 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1550676597 |
|
|
Jul 31 07:30:26 PM PDT 24 |
Jul 31 07:30:40 PM PDT 24 |
17777400 ps |
| T1178 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1163357014 |
|
|
Jul 31 07:31:03 PM PDT 24 |
Jul 31 07:31:19 PM PDT 24 |
14363000 ps |
| T1179 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2097930522 |
|
|
Jul 31 07:30:23 PM PDT 24 |
Jul 31 07:31:08 PM PDT 24 |
341051600 ps |
| T323 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1745769752 |
|
|
Jul 31 07:30:50 PM PDT 24 |
Jul 31 07:31:07 PM PDT 24 |
229361800 ps |
| T242 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1503219207 |
|
|
Jul 31 07:30:42 PM PDT 24 |
Jul 31 07:30:56 PM PDT 24 |
18167200 ps |
| T1180 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.772961938 |
|
|
Jul 31 07:31:02 PM PDT 24 |
Jul 31 07:31:15 PM PDT 24 |
21368700 ps |
| T1181 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2257670679 |
|
|
Jul 31 07:30:44 PM PDT 24 |
Jul 31 07:30:58 PM PDT 24 |
21668600 ps |
| T1182 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.275507161 |
|
|
Jul 31 07:31:05 PM PDT 24 |
Jul 31 07:31:18 PM PDT 24 |
55809300 ps |
| T1183 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.206515211 |
|
|
Jul 31 07:30:22 PM PDT 24 |
Jul 31 07:30:38 PM PDT 24 |
32511500 ps |
| T1184 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2992681063 |
|
|
Jul 31 07:31:02 PM PDT 24 |
Jul 31 07:31:17 PM PDT 24 |
532604400 ps |
| T256 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.4099637405 |
|
|
Jul 31 07:30:48 PM PDT 24 |
Jul 31 07:31:07 PM PDT 24 |
54140600 ps |
| T1185 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1468010922 |
|
|
Jul 31 07:30:39 PM PDT 24 |
Jul 31 07:30:57 PM PDT 24 |
112163300 ps |
| T260 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1896790969 |
|
|
Jul 31 07:30:57 PM PDT 24 |
Jul 31 07:31:13 PM PDT 24 |
127051200 ps |
| T1186 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.1047063917 |
|
|
Jul 31 07:30:29 PM PDT 24 |
Jul 31 07:30:43 PM PDT 24 |
17929300 ps |
| T1187 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1376992303 |
|
|
Jul 31 07:30:31 PM PDT 24 |
Jul 31 07:32:02 PM PDT 24 |
17209028300 ps |
| T1188 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3589373748 |
|
|
Jul 31 07:30:52 PM PDT 24 |
Jul 31 07:31:08 PM PDT 24 |
68340300 ps |
| T264 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3401331174 |
|
|
Jul 31 07:30:57 PM PDT 24 |
Jul 31 07:31:17 PM PDT 24 |
262567300 ps |
| T1189 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2229195481 |
|
|
Jul 31 07:30:57 PM PDT 24 |
Jul 31 07:31:14 PM PDT 24 |
82356300 ps |
| T262 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.4005296731 |
|
|
Jul 31 07:30:45 PM PDT 24 |
Jul 31 07:31:06 PM PDT 24 |
246957600 ps |
| T1190 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1381737279 |
|
|
Jul 31 07:30:42 PM PDT 24 |
Jul 31 07:30:59 PM PDT 24 |
40540000 ps |
| T1191 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2962806769 |
|
|
Jul 31 07:30:40 PM PDT 24 |
Jul 31 07:30:57 PM PDT 24 |
144749400 ps |
| T266 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2192538785 |
|
|
Jul 31 07:31:04 PM PDT 24 |
Jul 31 07:31:21 PM PDT 24 |
67826600 ps |
| T1192 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.232581509 |
|
|
Jul 31 07:31:20 PM PDT 24 |
Jul 31 07:31:33 PM PDT 24 |
52684700 ps |
| T1193 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.47414703 |
|
|
Jul 31 07:31:18 PM PDT 24 |
Jul 31 07:31:32 PM PDT 24 |
116350800 ps |
| T1194 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2223186728 |
|
|
Jul 31 07:31:03 PM PDT 24 |
Jul 31 07:31:16 PM PDT 24 |
21063400 ps |
| T1195 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3836686220 |
|
|
Jul 31 07:30:29 PM PDT 24 |
Jul 31 07:31:10 PM PDT 24 |
5484741400 ps |
| T1196 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1281329337 |
|
|
Jul 31 07:31:01 PM PDT 24 |
Jul 31 07:31:17 PM PDT 24 |
124108500 ps |
| T1197 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.505876869 |
|
|
Jul 31 07:30:55 PM PDT 24 |
Jul 31 07:31:14 PM PDT 24 |
419058300 ps |
| T1198 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3121332566 |
|
|
Jul 31 07:31:20 PM PDT 24 |
Jul 31 07:31:33 PM PDT 24 |
44526300 ps |
| T1199 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3475834826 |
|
|
Jul 31 07:31:19 PM PDT 24 |
Jul 31 07:31:33 PM PDT 24 |
82023800 ps |
| T1200 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.1312253048 |
|
|
Jul 31 07:31:21 PM PDT 24 |
Jul 31 07:31:35 PM PDT 24 |
17693600 ps |
| T1201 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.2374094882 |
|
|
Jul 31 07:31:16 PM PDT 24 |
Jul 31 07:31:29 PM PDT 24 |
22175100 ps |
| T1202 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.878570682 |
|
|
Jul 31 07:31:03 PM PDT 24 |
Jul 31 07:31:17 PM PDT 24 |
32430200 ps |
| T379 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1791542700 |
|
|
Jul 31 07:31:06 PM PDT 24 |
Jul 31 07:38:43 PM PDT 24 |
261621600 ps |
| T268 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2311135048 |
|
|
Jul 31 07:30:43 PM PDT 24 |
Jul 31 07:31:00 PM PDT 24 |
42443100 ps |
| T1203 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1896724555 |
|
|
Jul 31 07:30:30 PM PDT 24 |
Jul 31 07:30:45 PM PDT 24 |
20991200 ps |
| T1204 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3037004561 |
|
|
Jul 31 07:31:15 PM PDT 24 |
Jul 31 07:31:29 PM PDT 24 |
15286900 ps |
| T265 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1846220987 |
|
|
Jul 31 07:30:29 PM PDT 24 |
Jul 31 07:30:50 PM PDT 24 |
234376800 ps |
| T1205 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1352838219 |
|
|
Jul 31 07:30:30 PM PDT 24 |
Jul 31 07:30:43 PM PDT 24 |
17844700 ps |
| T1206 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2168983934 |
|
|
Jul 31 07:31:06 PM PDT 24 |
Jul 31 07:31:23 PM PDT 24 |
61809100 ps |
| T375 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3821068123 |
|
|
Jul 31 07:30:41 PM PDT 24 |
Jul 31 07:38:28 PM PDT 24 |
213227100 ps |
| T1207 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.4076212989 |
|
|
Jul 31 07:30:30 PM PDT 24 |
Jul 31 07:31:24 PM PDT 24 |
2122956800 ps |
| T1208 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.172105807 |
|
|
Jul 31 07:30:33 PM PDT 24 |
Jul 31 07:30:47 PM PDT 24 |
15728300 ps |
| T378 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3109696123 |
|
|
Jul 31 07:31:02 PM PDT 24 |
Jul 31 07:43:40 PM PDT 24 |
2067142300 ps |
| T1209 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.4067478855 |
|
|
Jul 31 07:30:48 PM PDT 24 |
Jul 31 07:31:04 PM PDT 24 |
148063600 ps |
| T275 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1008253380 |
|
|
Jul 31 07:30:57 PM PDT 24 |
Jul 31 07:43:29 PM PDT 24 |
1334065300 ps |
| T380 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.22695618 |
|
|
Jul 31 07:30:31 PM PDT 24 |
Jul 31 07:37:05 PM PDT 24 |
349986300 ps |
| T1210 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.4149044297 |
|
|
Jul 31 07:30:52 PM PDT 24 |
Jul 31 07:31:09 PM PDT 24 |
165003800 ps |
| T1211 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2110703353 |
|
|
Jul 31 07:30:41 PM PDT 24 |
Jul 31 07:30:58 PM PDT 24 |
66473800 ps |
| T1212 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3935033148 |
|
|
Jul 31 07:30:22 PM PDT 24 |
Jul 31 07:30:38 PM PDT 24 |
36155700 ps |
| T1213 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.4101509785 |
|
|
Jul 31 07:30:50 PM PDT 24 |
Jul 31 07:31:06 PM PDT 24 |
11811400 ps |
| T1214 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1899702688 |
|
|
Jul 31 07:31:02 PM PDT 24 |
Jul 31 07:31:18 PM PDT 24 |
69618200 ps |
| T1215 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2670353694 |
|
|
Jul 31 07:31:15 PM PDT 24 |
Jul 31 07:31:29 PM PDT 24 |
57110900 ps |
| T1216 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2988028317 |
|
|
Jul 31 07:31:14 PM PDT 24 |
Jul 31 07:31:28 PM PDT 24 |
30240600 ps |
| T1217 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.3872361375 |
|
|
Jul 31 07:31:19 PM PDT 24 |
Jul 31 07:31:32 PM PDT 24 |
15335900 ps |
| T272 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3620838614 |
|
|
Jul 31 07:30:59 PM PDT 24 |
Jul 31 07:31:15 PM PDT 24 |
143608700 ps |
| T1218 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3580620505 |
|
|
Jul 31 07:30:59 PM PDT 24 |
Jul 31 07:31:13 PM PDT 24 |
24536100 ps |
| T1219 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2736485580 |
|
|
Jul 31 07:30:43 PM PDT 24 |
Jul 31 07:30:59 PM PDT 24 |
20060800 ps |
| T1220 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1250373464 |
|
|
Jul 31 07:31:03 PM PDT 24 |
Jul 31 07:38:36 PM PDT 24 |
852729100 ps |
| T1221 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.422130979 |
|
|
Jul 31 07:30:51 PM PDT 24 |
Jul 31 07:31:08 PM PDT 24 |
78807900 ps |
| T1222 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1446314529 |
|
|
Jul 31 07:30:42 PM PDT 24 |
Jul 31 07:31:00 PM PDT 24 |
35234700 ps |
| T1223 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1577416041 |
|
|
Jul 31 07:30:59 PM PDT 24 |
Jul 31 07:31:16 PM PDT 24 |
86625600 ps |
| T1224 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.4039020486 |
|
|
Jul 31 07:30:44 PM PDT 24 |
Jul 31 07:30:58 PM PDT 24 |
122431000 ps |
| T243 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.541062414 |
|
|
Jul 31 07:30:22 PM PDT 24 |
Jul 31 07:30:36 PM PDT 24 |
19341300 ps |
| T1225 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3635093599 |
|
|
Jul 31 07:31:02 PM PDT 24 |
Jul 31 07:31:18 PM PDT 24 |
38090200 ps |
| T1226 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.947509187 |
|
|
Jul 31 07:30:32 PM PDT 24 |
Jul 31 07:31:38 PM PDT 24 |
662963700 ps |
| T1227 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.905595083 |
|
|
Jul 31 07:30:44 PM PDT 24 |
Jul 31 07:31:00 PM PDT 24 |
14491700 ps |
| T1228 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1964406382 |
|
|
Jul 31 07:30:54 PM PDT 24 |
Jul 31 07:31:10 PM PDT 24 |
256119600 ps |
| T1229 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3341572908 |
|
|
Jul 31 07:30:24 PM PDT 24 |
Jul 31 07:30:43 PM PDT 24 |
102230900 ps |
| T1230 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2035077519 |
|
|
Jul 31 07:31:04 PM PDT 24 |
Jul 31 07:31:17 PM PDT 24 |
14702800 ps |
| T1231 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2721209756 |
|
|
Jul 31 07:30:32 PM PDT 24 |
Jul 31 07:30:46 PM PDT 24 |
96661800 ps |
| T1232 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.2975700139 |
|
|
Jul 31 07:30:31 PM PDT 24 |
Jul 31 07:30:45 PM PDT 24 |
51351000 ps |
| T1233 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.690554641 |
|
|
Jul 31 07:31:00 PM PDT 24 |
Jul 31 07:31:16 PM PDT 24 |
42066100 ps |
| T1234 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.901929042 |
|
|
Jul 31 07:30:31 PM PDT 24 |
Jul 31 07:30:47 PM PDT 24 |
172870000 ps |
| T1235 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3822834149 |
|
|
Jul 31 07:30:53 PM PDT 24 |
Jul 31 07:31:10 PM PDT 24 |
107749300 ps |
| T1236 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.4126840394 |
|
|
Jul 31 07:31:04 PM PDT 24 |
Jul 31 07:31:18 PM PDT 24 |
11031600 ps |
| T374 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3273738225 |
|
|
Jul 31 07:30:44 PM PDT 24 |
Jul 31 07:38:26 PM PDT 24 |
1368667600 ps |
| T1237 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1596860552 |
|
|
Jul 31 07:30:51 PM PDT 24 |
Jul 31 07:31:05 PM PDT 24 |
26302300 ps |
| T1238 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2080376195 |
|
|
Jul 31 07:30:57 PM PDT 24 |
Jul 31 07:31:13 PM PDT 24 |
14924600 ps |
| T1239 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1484923613 |
|
|
Jul 31 07:30:28 PM PDT 24 |
Jul 31 07:30:41 PM PDT 24 |
16012000 ps |
| T1240 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3478472037 |
|
|
Jul 31 07:31:02 PM PDT 24 |
Jul 31 07:31:20 PM PDT 24 |
51612100 ps |
| T1241 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2317011774 |
|
|
Jul 31 07:31:16 PM PDT 24 |
Jul 31 07:31:30 PM PDT 24 |
189207000 ps |
| T1242 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.4072640377 |
|
|
Jul 31 07:30:52 PM PDT 24 |
Jul 31 07:31:05 PM PDT 24 |
87730900 ps |
| T1243 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.766004242 |
|
|
Jul 31 07:30:30 PM PDT 24 |
Jul 31 07:30:48 PM PDT 24 |
46779100 ps |
| T1244 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3600200688 |
|
|
Jul 31 07:30:42 PM PDT 24 |
Jul 31 07:30:57 PM PDT 24 |
52475000 ps |
| T1245 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1228564567 |
|
|
Jul 31 07:30:43 PM PDT 24 |
Jul 31 07:30:58 PM PDT 24 |
43420900 ps |
| T1246 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2232974574 |
|
|
Jul 31 07:30:46 PM PDT 24 |
Jul 31 07:31:01 PM PDT 24 |
14012000 ps |
| T1247 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.109094516 |
|
|
Jul 31 07:31:06 PM PDT 24 |
Jul 31 07:31:40 PM PDT 24 |
60942400 ps |
| T1248 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.4119258889 |
|
|
Jul 31 07:31:03 PM PDT 24 |
Jul 31 07:31:24 PM PDT 24 |
256004400 ps |
| T1249 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3779476438 |
|
|
Jul 31 07:31:15 PM PDT 24 |
Jul 31 07:31:29 PM PDT 24 |
17066500 ps |
| T1250 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3883735145 |
|
|
Jul 31 07:30:59 PM PDT 24 |
Jul 31 07:31:15 PM PDT 24 |
25175500 ps |
| T1251 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3522520879 |
|
|
Jul 31 07:30:53 PM PDT 24 |
Jul 31 07:31:06 PM PDT 24 |
109291700 ps |