Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	359530	1		T1	2		T2	2		T3	1
all_values[1]	359530	1		T1	2		T2	2		T3	1
all_values[2]	359530	1		T1	2		T2	2		T3	1
all_values[3]	359530	1		T1	2		T2	2		T3	1
all_values[4]	359530	1		T1	2		T2	2		T3	1
all_values[5]	359530	1		T1	2		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	725438	1		T1	12		T2	12		T3	6
auto[1]	1431742	1		T4	2000		T32	12584		T34	4040

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1054239	1		T1	7		T2	7		T3	4
auto[1]	1102941	1		T1	5		T2	5		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	359365	1		T1	2		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	165	1		T266	6		T267	5		T268	7
all_values[1]	auto[0]	auto[1]	359365	1		T1	2		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	165	1		T266	7		T267	5		T268	3
all_values[2]	auto[0]	auto[0]	1617	1		T1	2		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	58	1		T266	3		T267	2		T268	2
all_values[2]	auto[1]	auto[0]	357800	1		T4	500		T32	3146		T34	1010
all_values[2]	auto[1]	auto[1]	55	1		T267	3		T268	2		T330	2
all_values[3]	auto[0]	auto[0]	1612	1		T1	2		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	69	1		T266	3		T267	2		T268	3
all_values[3]	auto[1]	auto[0]	84304	1		T4	82		T32	1573		T34	505
all_values[3]	auto[1]	auto[1]	273545	1		T4	418		T32	1573		T34	505
all_values[4]	auto[0]	auto[0]	1156	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	532	1		T1	1		T2	1		T11	1
all_values[4]	auto[1]	auto[0]	248381	1		T4	416		T32	1573		T34	505
all_values[4]	auto[1]	auto[1]	109461	1		T4	84		T32	1573		T34	505
all_values[5]	auto[0]	auto[0]	1575	1		T1	2		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	89	1		T36	1		T37	1		T38	1
all_values[5]	auto[1]	auto[0]	357794	1		T4	500		T32	3146		T34	1010
all_values[5]	auto[1]	auto[1]	72	1		T266	3		T267	2		T268	2