Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	1	15	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	1	15	93.75	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	245243	1		T1	600		T2	2		T11	1
auto[FlashEraseBank]	272472	1		T11	1		T4	37		T23	16

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	259947	1		T1	200		T2	1		T11	1
auto[FlashOpProgram]	237966	1		T1	100		T5	179		T21	1
auto[FlashOpErase]	15802	1		T1	100		T2	1		T11	1
auto[FlashOpInvalid]	4000	1		T1	200		T134	200		T221	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	259947	1		T1	200		T2	1		T11	1
op[FlashOpProgram]	237966	1		T1	100		T5	179		T21	1
op[FlashOpErase]	15802	1		T1	100		T2	1		T11	1
read_erase_read	566	1		T23	17		T31	4		T33	1
read_prog_read	839	1		T26	1		T22	8		T40	1

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	376215	1		T1	588		T2	1		T11	1
auto[FlashPartInfo]	137779	1		T1	12		T2	1		T11	1
auto[FlashPartInfo1]	861	1		T4	21		T41	1		T24	64
auto[FlashPartInfo2]	2860	1		T4	63		T21	1		T41	10

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for op_part_cross

Uncovered bins

part_cp	op_cp	COUNT	AT LEAST	NUMBER
[auto[FlashPartInfo1]]	[auto[FlashOpInvalid]]	0	1	1

Covered bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	190313	1		T1	196		T11	1		T23	8
auto[FlashPartData]	auto[FlashOpProgram]	178390	1		T1	98		T7	2		T6	8
auto[FlashPartData]	auto[FlashOpErase]	3606	1		T1	98		T2	1		T23	9
auto[FlashPartData]	auto[FlashOpInvalid]	3906	1		T1	196		T134	194		T221	198
auto[FlashPartInfo]	auto[FlashOpRead]	67128	1		T1	4		T2	1		T5	368
auto[FlashPartInfo]	auto[FlashOpProgram]	58403	1		T1	2		T5	179		T26	1
auto[FlashPartInfo]	auto[FlashOpErase]	12168	1		T1	2		T11	1		T5	179
auto[FlashPartInfo]	auto[FlashOpInvalid]	80	1		T1	4		T134	6		T221	2
auto[FlashPartInfo1]	auto[FlashOpRead]	697	1		T4	21		T41	1		T24	32
auto[FlashPartInfo1]	auto[FlashOpProgram]	161	1		T24	32		T137	32		T138	32
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T345	1		T346	1		T347	1
auto[FlashPartInfo2]	auto[FlashOpRead]	1809	1		T4	63		T41	10		T24	64
auto[FlashPartInfo2]	auto[FlashOpProgram]	1012	1		T21	1		T24	64		T127	7
auto[FlashPartInfo2]	auto[FlashOpErase]	25	1		T132	1		T133	1		T135	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	14	1		T348	2		T349	2		T350	2