Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30999	1		T1	400		T5	348		T23	5
auto[1]	58	1		T133	14		T144	1		T395	1
auto[2]	61	1		T396	1		T294	8		T397	1
auto[3]	251	1		T23	11		T210	1		T132	15

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7845	1		T1	100		T5	87		T23	6
evic_idx[1]	7845	1		T1	100		T5	87		T23	3
evic_idx[2]	7845	1		T1	100		T5	87		T23	3
evic_idx[3]	7834	1		T1	100		T5	87		T23	4

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30383	1		T1	400		T5	348		T23	16
evic_op[2]	378	1		T6	1		T31	4		T69	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7527	1		T1	100		T5	87		T23	1
evic_idx[0]	evic_op[1]	auto[1]	12	1		T133	4		T398	3		T399	2
evic_idx[0]	evic_op[1]	auto[2]	10	1		T294	4		T400	5		T401	1
evic_idx[0]	evic_op[1]	auto[3]	59	1		T23	5		T132	4		T224	1
evic_idx[0]	evic_op[2]	auto[0]	73	1		T31	1		T69	1		T317	1
evic_idx[0]	evic_op[2]	auto[1]	1	1		T82	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[2]	2	1		T402	1		T403	1		-	-
evic_idx[0]	evic_op[2]	auto[3]	8	1		T112	1		T404	1		T405	1
evic_idx[1]	evic_op[1]	auto[0]	7522	1		T1	100		T5	87		T23	1
evic_idx[1]	evic_op[1]	auto[1]	13	1		T133	3		T398	4		T399	3
evic_idx[1]	evic_op[1]	auto[2]	8	1		T294	1		T406	1		T407	1
evic_idx[1]	evic_op[1]	auto[3]	54	1		T23	2		T132	4		T133	1
evic_idx[1]	evic_op[2]	auto[0]	77	1		T6	1		T31	1		T317	1
evic_idx[1]	evic_op[2]	auto[1]	6	1		T144	1		T395	1		T408	1
evic_idx[1]	evic_op[2]	auto[2]	4	1		T397	1		T409	1		T410	1
evic_idx[1]	evic_op[2]	auto[3]	9	1		T411	1		T412	1		T413	1
evic_idx[2]	evic_op[1]	auto[0]	7524	1		T1	100		T5	87		T23	1
evic_idx[2]	evic_op[1]	auto[1]	11	1		T133	4		T398	2		T399	2
evic_idx[2]	evic_op[1]	auto[2]	9	1		T294	2		T406	1		T407	1
evic_idx[2]	evic_op[1]	auto[3]	52	1		T23	2		T132	3		T224	3
evic_idx[2]	evic_op[2]	auto[0]	78	1		T31	1		T71	1		T317	1
evic_idx[2]	evic_op[2]	auto[1]	5	1		T82	1		T414	1		T415	1
evic_idx[2]	evic_op[2]	auto[2]	2	1		T402	1		T409	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	12	1		T321	1		T416	1		T417	1
evic_idx[3]	evic_op[1]	auto[0]	7526	1		T1	100		T5	87		T23	2
evic_idx[3]	evic_op[1]	auto[1]	7	1		T133	3		T398	1		T399	2
evic_idx[3]	evic_op[1]	auto[2]	7	1		T294	1		T398	1		T418	1
evic_idx[3]	evic_op[1]	auto[3]	42	1		T23	2		T132	4		T294	3
evic_idx[3]	evic_op[2]	auto[0]	76	1		T31	1		T317	1		T396	1
evic_idx[3]	evic_op[2]	auto[1]	3	1		T82	1		T419	1		T420	1
evic_idx[3]	evic_op[2]	auto[2]	7	1		T396	1		T402	1		T409	1
evic_idx[3]	evic_op[2]	auto[3]	15	1		T210	1		T396	1		T421	1