Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	35862	1		T240	16353		T334	14308		T335	2700
rd_lvl[2]	45034	1		T240	11951		T334	10396		T336	1518
rd_lvl[3]	12006	1		T4	336		T337	935		T336	1898
rd_lvl[4]	16314	1		T4	77		T289	1442		T337	1022
rd_lvl[5]	22550	1		T291	828		T231	2346		T338	2315
rd_lvl[6]	38206	1		T4	2		T291	212		T231	1127
rd_lvl[7]	13596	1		T4	2		T281	144		T289	51
rd_lvl[8]	16910	1		T291	109		T230	1605		T326	3164
rd_lvl[9]	7120	1		T230	169		T326	300		T281	110
rd_lvl[10]	4188	1		T217	144		T281	109		T339	1351
rd_lvl[11]	4317	1		T34	260		T158	60		T291	106
rd_lvl[12]	6443	1		T34	120		T158	12		T286	1142
rd_lvl[13]	3097	1		T34	1		T35	219		T340	243
rd_lvl[14]	5375	1		T32	1174		T34	124		T35	206
rd_lvl[15]	2229	1		T32	399		T320	379		T341	2