Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	359530	1		T1	2		T2	2		T3	1
all_pins[1]	359530	1		T1	2		T2	2		T3	1
all_pins[2]	359530	1		T1	2		T2	2		T3	1
all_pins[3]	359530	1		T1	2		T2	2		T3	1
all_pins[4]	359530	1		T1	2		T2	2		T3	1
all_pins[5]	359530	1		T1	2		T2	2		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1797177	1		T1	12		T2	12		T3	6
values[0x1]	360003	1		T4	519		T32	3146		T34	1010
transitions[0x0=>0x1]	321954	1		T4	499		T32	3146		T34	1010
transitions[0x1=>0x0]	321940	1		T4	499		T32	3146		T34	1010

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	359365	1		T1	2		T2	2		T3	1
all_pins[0]	values[0x1]	165	1		T266	6		T267	5		T268	7
all_pins[0]	transitions[0x0=>0x1]	71	1		T266	1		T267	1		T268	4
all_pins[0]	transitions[0x1=>0x0]	71	1		T266	2		T267	1		T330	2
all_pins[1]	values[0x0]	359365	1		T1	2		T2	2		T3	1
all_pins[1]	values[0x1]	165	1		T266	7		T267	5		T268	3
all_pins[1]	transitions[0x0=>0x1]	133	1		T266	7		T267	3		T268	1
all_pins[1]	transitions[0x1=>0x0]	3327	1		T320	607		T351	28		T352	1198
all_pins[2]	values[0x0]	356171	1		T1	2		T2	2		T3	1
all_pins[2]	values[0x1]	3359	1		T320	607		T351	28		T352	1198
all_pins[2]	transitions[0x0=>0x1]	44	1		T267	3		T268	2		T330	2
all_pins[2]	transitions[0x1=>0x0]	233792	1		T4	417		T32	1573		T34	505
all_pins[3]	values[0x0]	122423	1		T1	2		T2	2		T3	1
all_pins[3]	values[0x1]	237107	1		T4	417		T32	1573		T34	505
all_pins[3]	transitions[0x0=>0x1]	202550	1		T4	397		T32	1573		T34	505
all_pins[3]	transitions[0x1=>0x0]	84578	1		T4	82		T32	1573		T34	505
all_pins[4]	values[0x0]	240395	1		T1	2		T2	2		T3	1
all_pins[4]	values[0x1]	119135	1		T4	102		T32	1573		T34	505
all_pins[4]	transitions[0x0=>0x1]	119125	1		T4	102		T32	1573		T34	505
all_pins[4]	transitions[0x1=>0x0]	62	1		T266	2		T268	2		T330	2
all_pins[5]	values[0x0]	359458	1		T1	2		T2	2		T3	1
all_pins[5]	values[0x1]	72	1		T266	3		T267	2		T268	2
all_pins[5]	transitions[0x0=>0x1]	31	1		T266	2		T330	1		T353	2
all_pins[5]	transitions[0x1=>0x0]	110	1		T266	4		T267	3		T268	5