Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1		T266	7		T267	7		T268	7
all_values[1]	284	1		T266	7		T267	7		T268	7
all_values[2]	284	1		T266	7		T267	7		T268	7
all_values[3]	284	1		T266	7		T267	7		T268	7
all_values[4]	284	1		T266	7		T267	7		T268	7
all_values[5]	284	1		T266	7		T267	7		T268	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	949	1		T266	19		T267	21		T268	23
auto[1]	755	1		T266	23		T267	21		T268	19

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	566	1		T266	13		T267	9		T268	9
auto[1]	1138	1		T266	29		T267	33		T268	33

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1004	1		T266	24		T267	23		T268	22
auto[1]	700	1		T266	18		T267	19		T268	20

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	93	1		T266	1		T267	1		T268	2
all_values[0]	auto[0]	auto[1]	auto[1]	76	1		T266	3		T267	4		T268	1
all_values[0]	auto[1]	auto[0]	auto[1]	66	1		T266	1		T267	2		T330	2
all_values[0]	auto[1]	auto[1]	auto[1]	49	1		T266	2		T268	4		T330	2
all_values[1]	auto[0]	auto[0]	auto[1]	98	1		T266	1		T267	4		T268	2
all_values[1]	auto[0]	auto[1]	auto[1]	73	1		T266	3		T267	2		T268	4
all_values[1]	auto[1]	auto[0]	auto[1]	47	1		T266	1		T268	1		T330	1
all_values[1]	auto[1]	auto[1]	auto[1]	66	1		T266	2		T267	1		T330	1
all_values[2]	auto[0]	auto[0]	auto[0]	93	1		T266	3		T268	3		T330	3
all_values[2]	auto[0]	auto[1]	auto[0]	78	1		T266	1		T267	2		T330	1
all_values[2]	auto[1]	auto[0]	auto[1]	66	1		T266	3		T267	1		T268	1
all_values[2]	auto[1]	auto[1]	auto[1]	47	1		T267	4		T268	3		T330	1
all_values[3]	auto[0]	auto[0]	auto[0]	92	1		T267	3		T268	3		T330	2
all_values[3]	auto[0]	auto[1]	auto[0]	74	1		T266	2		T267	2		T330	1
all_values[3]	auto[1]	auto[0]	auto[1]	73	1		T266	4		T267	1		T268	3
all_values[3]	auto[1]	auto[1]	auto[1]	45	1		T266	1		T267	1		T268	1
all_values[4]	auto[0]	auto[0]	auto[0]	77	1		T266	2		T267	1		T268	1
all_values[4]	auto[0]	auto[0]	auto[1]	31	1		T266	1		T267	1		T330	1
all_values[4]	auto[0]	auto[1]	auto[0]	43	1		T266	2		T268	2		T330	2
all_values[4]	auto[0]	auto[1]	auto[1]	19	1		T331	2		T332	1		T333	1
all_values[4]	auto[1]	auto[0]	auto[1]	69	1		T267	2		T268	2		T330	1
all_values[4]	auto[1]	auto[1]	auto[1]	45	1		T266	2		T267	3		T268	2
all_values[5]	auto[0]	auto[0]	auto[0]	61	1		T266	1		T267	1		T330	1
all_values[5]	auto[0]	auto[0]	auto[1]	20	1		T267	1		T268	3		T330	1
all_values[5]	auto[0]	auto[1]	auto[0]	48	1		T266	2		T330	1		T331	2
all_values[5]	auto[0]	auto[1]	auto[1]	28	1		T266	2		T267	1		T268	1
all_values[5]	auto[1]	auto[0]	auto[1]	63	1		T266	1		T267	3		T268	2
all_values[5]	auto[1]	auto[1]	auto[1]	64	1		T266	1		T267	1		T268	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal