Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	303679	1		T1	1394		T2	1		T3	2
all_values[1]	303679	1		T1	1394		T2	1		T3	2
all_values[2]	303679	1		T1	1394		T2	1		T3	2
all_values[3]	303679	1		T1	1394		T2	1		T3	2
all_values[4]	303679	1		T1	1394		T2	1		T3	2
all_values[5]	303679	1		T1	1394		T2	1		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	613910	1		T1	2788		T2	6		T3	12
auto[1]	1208164	1		T1	5576		T24	6416		T8	544

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	892268	1		T1	4183		T2	4		T3	7
auto[1]	929806	1		T1	4181		T2	2		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	303533	1		T1	1394		T2	1		T3	2
all_values[0]	auto[1]	auto[1]	146	1		T253	1		T254	1		T255	3
all_values[1]	auto[0]	auto[1]	303536	1		T1	1394		T2	1		T3	2
all_values[1]	auto[1]	auto[1]	143	1		T253	2		T254	1		T255	4
all_values[2]	auto[0]	auto[0]	1660	1		T2	1		T3	2		T12	1
all_values[2]	auto[0]	auto[1]	58	1		T253	2		T255	3		T327	2
all_values[2]	auto[1]	auto[0]	301914	1		T1	1394		T24	1604		T8	136
all_values[2]	auto[1]	auto[1]	47	1		T254	2		T327	2		T328	1
all_values[3]	auto[0]	auto[0]	1662	1		T2	1		T3	2		T12	1
all_values[3]	auto[0]	auto[1]	51	1		T253	1		T255	1		T327	3
all_values[3]	auto[1]	auto[0]	84838	1		T1	1394		T24	1604		T33	1669
all_values[3]	auto[1]	auto[1]	217128	1		T8	136		T33	1669		T31	1843
all_values[4]	auto[0]	auto[0]	1183	1		T2	1		T3	1		T12	1
all_values[4]	auto[0]	auto[1]	529	1		T3	1		T4	9		T19	1
all_values[4]	auto[1]	auto[0]	197484	1		T1	1		T24	1		T8	68
all_values[4]	auto[1]	auto[1]	104483	1		T1	1393		T24	1603		T8	68
all_values[5]	auto[0]	auto[0]	1614	1		T2	1		T3	2		T12	1
all_values[5]	auto[0]	auto[1]	84	1		T35	1		T36	1		T98	1
all_values[5]	auto[1]	auto[0]	301913	1		T1	1394		T24	1604		T8	136
all_values[5]	auto[1]	auto[1]	68	1		T253	4		T255	2		T327	1