Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	1	15	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	1	15	93.75	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	244441	1		T1	904		T3	216		T4	19
auto[FlashEraseBank]	265314	1		T1	489		T4	14		T19	218

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	257000	1		T3	14		T4	17		T5	301
auto[FlashOpProgram]	232280	1		T1	1393		T3	192		T4	14
auto[FlashOpErase]	16475	1		T3	10		T4	2		T5	151
auto[FlashOpInvalid]	4000	1		T140	200		T288	200		T289	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	257000	1		T3	14		T4	17		T5	301
op[FlashOpProgram]	232280	1		T1	1393		T3	192		T4	14
op[FlashOpErase]	16475	1		T3	10		T4	2		T5	151
read_erase_read	541	1		T3	2		T4	2		T74	2
read_prog_read	834	1		T4	2		T19	1		T7	1

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	364242	1		T1	1166		T4	33		T19	573
auto[FlashPartInfo]	141399	1		T1	219		T3	216		T5	603
auto[FlashPartInfo1]	873	1		T74	9		T64	1		T157	2
auto[FlashPartInfo2]	3241	1		T1	8		T19	10		T24	7

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for op_part_cross

Uncovered bins

part_cp	op_cp	COUNT	AT LEAST	NUMBER
[auto[FlashPartInfo1]]	[auto[FlashOpInvalid]]	0	1	1

Covered bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	183310	1		T4	17		T19	105		T21	20
auto[FlashPartData]	auto[FlashOpProgram]	173427	1		T1	1166		T4	14		T19	468
auto[FlashPartData]	auto[FlashOpErase]	3579	1		T4	2		T6	1		T51	1
auto[FlashPartData]	auto[FlashOpInvalid]	3926	1		T140	198		T288	194		T289	198
auto[FlashPartInfo]	auto[FlashOpRead]	70790	1		T3	14		T5	301		T19	50
auto[FlashPartInfo]	auto[FlashOpProgram]	57687	1		T1	219		T3	192		T5	151
auto[FlashPartInfo]	auto[FlashOpErase]	12864	1		T3	10		T5	151		T49	311
auto[FlashPartInfo]	auto[FlashOpInvalid]	58	1		T140	2		T288	6		T289	2
auto[FlashPartInfo1]	auto[FlashOpRead]	708	1		T74	9		T64	1		T157	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	161	1		T63	32		T75	1		T124	32
auto[FlashPartInfo1]	auto[FlashOpErase]	4	1		T100	1		T125	1		T142	1
auto[FlashPartInfo2]	auto[FlashOpRead]	2192	1		T19	5		T8	68		T74	4
auto[FlashPartInfo2]	auto[FlashOpProgram]	1005	1		T1	8		T19	5		T24	7
auto[FlashPartInfo2]	auto[FlashOpErase]	28	1		T74	2		T139	2		T73	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	16	1		T149	4		T345	2		T346	2