Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32657	1		T4	4		T5	328		T49	624
auto[1]	54	1		T141	9		T395	7		T396	10
auto[2]	51	1		T158	8		T159	4		T396	11
auto[3]	325	1		T26	1		T27	1		T139	30

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8278	1		T4	1		T5	82		T49	156
evic_idx[1]	8264	1		T4	1		T5	82		T49	156
evic_idx[2]	8274	1		T4	1		T5	82		T49	156
evic_idx[3]	8271	1		T4	1		T5	82		T49	156

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	32156	1		T5	328		T49	624		T103	652
evic_op[2]	377	1		T6	1		T26	1		T72	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7955	1		T5	82		T49	156		T103	163
evic_idx[0]	evic_op[1]	auto[1]	11	1		T141	3		T396	2		T397	2
evic_idx[0]	evic_op[1]	auto[2]	5	1		T396	3		T398	2		-	-
evic_idx[0]	evic_op[1]	auto[3]	76	1		T139	9		T210	5		T141	4
evic_idx[0]	evic_op[2]	auto[0]	75	1		T30	2		T85	6		T118	1
evic_idx[0]	evic_op[2]	auto[1]	1	1		T399	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[2]	3	1		T400	1		T401	2		-	-
evic_idx[0]	evic_op[2]	auto[3]	13	1		T26	1		T199	1		T402	1
evic_idx[1]	evic_op[1]	auto[0]	7955	1		T5	82		T49	156		T103	163
evic_idx[1]	evic_op[1]	auto[1]	10	1		T141	2		T395	3		T396	1
evic_idx[1]	evic_op[1]	auto[2]	4	1		T396	3		T398	1		-	-
evic_idx[1]	evic_op[1]	auto[3]	67	1		T139	6		T210	2		T141	6
evic_idx[1]	evic_op[2]	auto[0]	73	1		T30	2		T85	6		T123	1
evic_idx[1]	evic_op[2]	auto[1]	2	1		T403	1		T399	1		-	-
evic_idx[1]	evic_op[2]	auto[2]	3	1		T401	1		T404	2		-	-
evic_idx[1]	evic_op[2]	auto[3]	11	1		T27	1		T138	1		T405	1
evic_idx[2]	evic_op[1]	auto[0]	7958	1		T5	82		T49	156		T103	163
evic_idx[2]	evic_op[1]	auto[1]	11	1		T141	2		T395	3		T396	4
evic_idx[2]	evic_op[1]	auto[2]	4	1		T396	3		T398	1		-	-
evic_idx[2]	evic_op[1]	auto[3]	62	1		T139	7		T210	3		T141	6
evic_idx[2]	evic_op[2]	auto[0]	78	1		T30	2		T85	6		T123	1
evic_idx[2]	evic_op[2]	auto[1]	3	1		T406	1		T407	1		T408	1
evic_idx[2]	evic_op[2]	auto[2]	2	1		T401	1		T409	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	17	1		T202	1		T138	2		T410	1
evic_idx[3]	evic_op[1]	auto[0]	7956	1		T5	82		T49	156		T103	163
evic_idx[3]	evic_op[1]	auto[1]	9	1		T141	2		T395	1		T396	3
evic_idx[3]	evic_op[1]	auto[2]	2	1		T396	2		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	71	1		T139	8		T210	3		T141	5
evic_idx[3]	evic_op[2]	auto[0]	77	1		T6	1		T72	1		T30	2
evic_idx[3]	evic_op[2]	auto[1]	7	1		T411	1		T412	1		T413	1
evic_idx[3]	evic_op[2]	auto[2]	4	1		T414	1		T404	1		T415	1
evic_idx[3]	evic_op[2]	auto[3]	8	1		T138	1		T416	1		T417	1