Summary for Variable instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for instr_type_cp
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others |
4751 |
1 |
|
T44 |
114 |
|
T45 |
54 |
|
T46 |
136 |
| instr_types[0] |
6024 |
1 |
|
T44 |
277 |
|
T45 |
243 |
|
T46 |
198 |
| instr_types[1] |
4146078 |
1 |
|
T4 |
50 |
|
T6 |
52 |
|
T7 |
193 |
Summary for Variable key_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for key_cp
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4154946 |
1 |
|
T4 |
50 |
|
T6 |
52 |
|
T7 |
193 |
| auto[1] |
1907 |
1 |
|
T44 |
177 |
|
T45 |
163 |
|
T46 |
221 |
Summary for Cross key_instr_cross
Samples crossed: key_cp instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins for key_instr_cross
Bins
| key_cp | instr_type_cp | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
others |
4392 |
1 |
|
T44 |
101 |
|
T45 |
39 |
|
T46 |
61 |
| auto[0] |
instr_types[0] |
5234 |
1 |
|
T44 |
190 |
|
T45 |
153 |
|
T46 |
105 |
| auto[0] |
instr_types[1] |
4145320 |
1 |
|
T4 |
50 |
|
T6 |
52 |
|
T7 |
193 |
| auto[1] |
others |
359 |
1 |
|
T44 |
13 |
|
T45 |
15 |
|
T46 |
75 |
| auto[1] |
instr_types[0] |
790 |
1 |
|
T44 |
87 |
|
T45 |
90 |
|
T46 |
93 |
| auto[1] |
instr_types[1] |
758 |
1 |
|
T44 |
77 |
|
T45 |
58 |
|
T46 |
53 |