Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	26615	1		T275	1997		T333	8500		T334	2539
rd_lvl[2]	23429	1		T335	6856		T275	902		T333	4620
rd_lvl[3]	14957	1		T52	1021		T156	4479		T335	228
rd_lvl[4]	36300	1		T52	1312		T156	4306		T336	5509
rd_lvl[5]	14656	1		T52	131		T213	532		T336	1179
rd_lvl[6]	9308	1		T52	64		T213	296		T275	3
rd_lvl[7]	6286	1		T52	28		T213	67		T337	1921
rd_lvl[8]	15889	1		T8	119		T52	11		T213	46
rd_lvl[9]	6428	1		T8	16		T33	520		T304	581
rd_lvl[10]	12598	1		T33	1149		T304	1035		T275	1
rd_lvl[11]	2763	1		T8	1		T213	50		T275	95
rd_lvl[12]	3061	1		T275	1		T338	1		T339	83
rd_lvl[13]	2182	1		T31	557		T52	39		T91	1
rd_lvl[14]	10721	1		T31	1286		T32	214		T275	95
rd_lvl[15]	4707	1		T32	177		T340	490		T341	227