Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	303679	1		T1	1394		T2	1		T3	2
all_pins[1]	303679	1		T1	1394		T2	1		T3	2
all_pins[2]	303679	1		T1	1394		T2	1		T3	2
all_pins[3]	303679	1		T1	1394		T2	1		T3	2
all_pins[4]	303679	1		T1	1394		T2	1		T3	2
all_pins[5]	303679	1		T1	1394		T2	1		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1508137	1		T1	6971		T2	6		T3	12
values[0x1]	313937	1		T1	1393		T24	1603		T8	204
transitions[0x0=>0x1]	279126	1		T1	1393		T24	1603		T8	136
transitions[0x1=>0x0]	279113	1		T1	1393		T24	1603		T8	136

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	303533	1		T1	1394		T2	1		T3	2
all_pins[0]	values[0x1]	146	1		T253	1		T254	1		T255	3
all_pins[0]	transitions[0x0=>0x1]	75	1		T254	1		T255	3		T327	1
all_pins[0]	transitions[0x1=>0x0]	72	1		T253	1		T254	1		T255	4
all_pins[1]	values[0x0]	303536	1		T1	1394		T2	1		T3	2
all_pins[1]	values[0x1]	143	1		T253	2		T254	1		T255	4
all_pins[1]	transitions[0x0=>0x1]	115	1		T253	2		T254	1		T255	4
all_pins[1]	transitions[0x1=>0x0]	3967	1		T32	172		T340	14		T341	349
all_pins[2]	values[0x0]	299684	1		T1	1394		T2	1		T3	2
all_pins[2]	values[0x1]	3995	1		T32	172		T340	14		T341	349
all_pins[2]	transitions[0x0=>0x1]	41	1		T254	2		T327	2		T330	1
all_pins[2]	transitions[0x1=>0x0]	189997	1		T8	136		T33	1669		T31	1843
all_pins[3]	values[0x0]	109728	1		T1	1394		T2	1		T3	2
all_pins[3]	values[0x1]	193951	1		T8	136		T33	1669		T31	1843
all_pins[3]	transitions[0x0=>0x1]	163249	1		T8	68		T33	1669		T31	1843
all_pins[3]	transitions[0x1=>0x0]	84932	1		T1	1393		T24	1603		T33	1669
all_pins[4]	values[0x0]	188045	1		T1	1		T2	1		T3	2
all_pins[4]	values[0x1]	115634	1		T1	1393		T24	1603		T8	68
all_pins[4]	transitions[0x0=>0x1]	115618	1		T1	1393		T24	1603		T8	68
all_pins[4]	transitions[0x1=>0x0]	52	1		T253	1		T255	2		T327	1
all_pins[5]	values[0x0]	303611	1		T1	1394		T2	1		T3	2
all_pins[5]	values[0x1]	68	1		T253	4		T255	2		T327	1
all_pins[5]	transitions[0x0=>0x1]	28	1		T253	2		T330	1		T347	1
all_pins[5]	transitions[0x1=>0x0]	93	1		T254	1		T255	1		T327	3